Commit a281d22b authored by Matthias Braun's avatar Matthias Braun
Browse files

refactor sparc nodes to have the same name as their assembler directives

[r27780]
parent 9c3d5824
......@@ -193,11 +193,11 @@ static void transform_Reload(ir_node *node)
ir_node *sched_point = sched_prev(node);
load = new_bd_sparc_Load(dbgi, block, ptr, mem, mode, entity, false, 0, true);
load = new_bd_sparc_Ld(dbgi, block, ptr, mem, mode, entity, false, 0, true);
sched_add_after(sched_point, load);
sched_remove(node);
proj = new_rd_Proj(dbgi, load, mode, pn_sparc_Load_res);
proj = new_rd_Proj(dbgi, load, mode, pn_sparc_Ld_res);
reg = arch_get_irn_register(node);
arch_set_irn_register(proj, reg);
......@@ -222,7 +222,7 @@ static void transform_Spill(ir_node *node)
ir_node *store;
sched_point = sched_prev(node);
store = new_bd_sparc_Store(dbgi, block, ptr, val, mem, mode, entity, false, 0, true);
store = new_bd_sparc_St(dbgi, block, ptr, val, mem, mode, entity, false, 0, true);
sched_remove(node);
sched_add_after(sched_point, store);
......
......@@ -586,7 +586,7 @@ static void emit_sparc_FrameAddr(const ir_node *irn)
/**
* Emits code for Branch
*/
static void emit_sparc_Branch(const ir_node *irn)
static void emit_sparc_BXX(const ir_node *irn)
{
const ir_edge_t *edge;
const ir_node *proj_true = NULL;
......@@ -671,7 +671,7 @@ static void emit_sparc_Branch(const ir_node *irn)
/**
* emit Jmp (which actually is a branch always (ba) instruction)
*/
static void emit_sparc_Jmp(const ir_node *node)
static void emit_sparc_Ba(const ir_node *node)
{
ir_node *block, *next_block;
......@@ -761,11 +761,11 @@ static void sparc_register_emitters(void)
set_emitter(op_be_MemPerm, emit_be_MemPerm);
set_emitter(op_be_Perm, emit_be_Perm);
set_emitter(op_be_Return, emit_be_Return);
set_emitter(op_sparc_Branch, emit_sparc_Branch);
set_emitter(op_sparc_BXX, emit_sparc_BXX);
set_emitter(op_sparc_Div, emit_sparc_Div);
set_emitter(op_sparc_FrameAddr, emit_sparc_FrameAddr);
set_emitter(op_sparc_HiImm, emit_sparc_HiImm);
set_emitter(op_sparc_Jmp, emit_sparc_Jmp);
set_emitter(op_sparc_Ba, emit_sparc_Ba);
set_emitter(op_sparc_LoImm, emit_sparc_LoImm);
set_emitter(op_sparc_Mul, emit_sparc_Mul);
set_emitter(op_sparc_Mulh, emit_sparc_Mulh);
......
......@@ -85,7 +85,7 @@ static void sparc_dump_node(FILE *F, ir_node *n, dump_reason_t reason)
fprintf(F, "fp_offset: 0x%X\n", attr->fp_offset);
}
if (is_sparc_Load(n) || is_sparc_Store(n)) {
if (is_sparc_Ld(n) || is_sparc_St(n)) {
const sparc_load_store_attr_t *attr = get_sparc_load_store_attr_const(n);
fprintf(F, "offset: 0x%lX\n", attr->offset);
fprintf(F, "is_frame_entity: %s\n", attr->is_frame_entity == true ? "true" : "false");
......@@ -183,13 +183,13 @@ const sparc_symconst_attr_t *get_sparc_symconst_attr_const(const ir_node *node)
sparc_jmp_cond_attr_t *get_sparc_jmp_cond_attr(ir_node *node)
{
assert(is_sparc_Branch(node) && "need sparc B node to get attributes");
assert(is_sparc_BXX(node) && "need sparc B node to get attributes");
return (sparc_jmp_cond_attr_t *)get_irn_generic_attr_const(node);
}
const sparc_jmp_cond_attr_t *get_sparc_jmp_cond_attr_const(const ir_node *node)
{
assert(is_sparc_Branch(node) && "need sparc B node to get attributes");
assert(is_sparc_BXX(node) && "need sparc B node to get attributes");
return (const sparc_jmp_cond_attr_t *)get_irn_generic_attr_const(node);
}
......
......@@ -219,7 +219,7 @@ Sub => {
# Load / Store
Load => {
Ld => {
op_flags => [ "labeled", "fragile" ],
state => "exc_pinned",
ins => [ "ptr", "mem" ],
......@@ -230,17 +230,6 @@ Load => {
emit => '. ld%LM [%S1%O], %D1'
},
LoadHi => {
op_flags => [ "labeled", "fragile" ],
state => "exc_pinned",
ins => [ "ptr", "mem" ],
outs => [ "res", "M" ],
reg_req => { in => [ "gp", "none" ], out => [ "gp", "none" ] },
attr_type => "sparc_load_store_attr_t",
attr => "ir_mode *ls_mode, ir_entity *entity, int entity_sign, long offset, bool is_frame_entity",
emit => '. sethi %%hi(%S1), %D1',
},
HiImm => {
irn_flags => [ "rematerializable" ],
state => "exc_pinned",
......@@ -264,18 +253,7 @@ LoImm => {
custominit => "sparc_set_attr_imm(res, immediate_value);",
},
LoadLo => {
op_flags => [ "labeled", "fragile" ],
state => "exc_pinned",
ins => [ "hireg", "ptr", "mem" ],
outs => [ "res", "M" ],
reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none" ] },
attr_type => "sparc_load_store_attr_t",
attr => "ir_mode *ls_mode, ir_entity *entity, int entity_sign, long offset, bool is_frame_entity",
emit => '. or %S1, %%lo(%S2), %D1'
},
Store => {
St => {
op_flags => [ "labeled", "fragile" ],
mode => "mode_M",
state => "exc_pinned",
......@@ -307,14 +285,14 @@ Save => {
init_attr => "\tinit_sparc_save_attr(res, initial_stacksize);",
},
AddSP => {
SubSP => {
reg_req => { in => [ "sp", "gp", "none" ], out => [ "sp:I|S", "gp", "none" ] },
ins => [ "stack", "size", "mem" ],
outs => [ "stack", "addr", "M" ],
emit => ". sub %S1, %S2, %D1\n",
},
SubSP => {
AddSP => {
reg_req => { in => [ "sp", "gp", "none" ], out => [ "sp:I|S", "none" ] },
ins => [ "stack", "size", "mem" ],
outs => [ "stack", "M" ],
......@@ -340,7 +318,7 @@ FrameAddr => {
mode => $mode_gp,
},
Branch => {
BXX => {
op_flags => [ "labeled", "cfopcode", "forking" ],
state => "pinned",
mode => "mode_T",
......@@ -350,7 +328,7 @@ Branch => {
init_attr => "\tset_sparc_jmp_cond_proj_num(res, proj_num);",
},
Jmp => {
Ba => {
state => "pinned",
op_flags => [ "cfopcode" ],
irn_flags => [ "simple_jump" ],
......@@ -388,7 +366,7 @@ SwitchJmp => {
attr_type => "sparc_jmp_switch_attr_t",
},
ShiftLL => {
Sll => {
irn_flags => [ "rematerializable" ],
mode => $mode_gp,
reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
......@@ -396,7 +374,7 @@ ShiftLL => {
constructors => \%binop_operand_constructors,
},
ShiftLR => {
Slr => {
irn_flags => [ "rematerializable" ],
mode => $mode_gp,
reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
......@@ -404,7 +382,7 @@ ShiftLR => {
constructors => \%binop_operand_constructors,
},
ShiftRA => {
Sra => {
irn_flags => [ "rematerializable" ],
mode => $mode_gp,
reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
......@@ -464,7 +442,6 @@ Div => {
Minus => {
irn_flags => [ "rematerializable" ],
mode => $mode_gp,
#reg_req => { in => [ "gp" ], out => [ "in_r1" ] },
reg_req => { in => [ "gp" ], out => [ "gp" ] },
emit => ". sub %%g0, %S1, %D1"
},
......@@ -501,39 +478,39 @@ fsMuld => {
emit =>'. fsmuld %S1, %S2, %D1'
},
FpSToFpD => {
FsTOd => {
irn_flags => [ "rematerializable" ],
reg_req => { in => [ "fp" ], out => [ "fp" ] },
emit =>'. FsTOd %S1, %D1'
},
FpDToFpS => {
FdTOs => {
irn_flags => [ "rematerializable" ],
reg_req => { in => [ "fp" ], out => [ "fp" ] },
emit =>'. FdTOs %S1, %D1'
},
FpSToInt => {
FiTOs => {
irn_flags => [ "rematerializable" ],
reg_req => { in => [ "fp" ], out => [ "gp" ] },
reg_req => { in => [ "gp" ], out => [ "fp" ] },
emit =>'. FiTOs %S1, %D1'
},
FpDToInt => {
FiTOd => {
irn_flags => [ "rematerializable" ],
reg_req => { in => [ "fp" ], out => [ "gp" ] },
reg_req => { in => [ "gp" ], out => [ "fp" ] },
emit =>'. FiTOd %S1, %D1'
},
IntToFpS => {
FsTOi => {
irn_flags => [ "rematerializable" ],
reg_req => { in => [ "gp" ], out => [ "fp" ] },
reg_req => { in => [ "fp" ], out => [ "gp" ] },
emit =>'. FsTOi %S1, %D1'
},
IntToFpD => {
FdTOi => {
irn_flags => [ "rematerializable" ],
reg_req => { in => [ "gp" ], out => [ "fp" ] },
reg_req => { in => [ "fp" ], out => [ "gp" ] },
emit =>'. FdTOi %S1, %D1'
},
......
......@@ -79,8 +79,8 @@ static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
if (src_bits == 8) {
return new_bd_sparc_And_imm(dbgi, block, op, 0xFF);
} else if (src_bits == 16) {
ir_node *lshift = new_bd_sparc_ShiftLL_imm(dbgi, block, op, 16);
ir_node *rshift = new_bd_sparc_ShiftLR_imm(dbgi, block, lshift, 16);
ir_node *lshift = new_bd_sparc_Sll_imm(dbgi, block, op, 16);
ir_node *rshift = new_bd_sparc_Slr_imm(dbgi, block, lshift, 16);
return rshift;
} else {
panic("zero extension only supported for 8 and 16 bits");
......@@ -94,8 +94,8 @@ static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
int src_bits)
{
int shift_width = 32 - src_bits;
ir_node *lshift_node = new_bd_sparc_ShiftLL_imm(dbgi, block, op, shift_width);
ir_node *rshift_node = new_bd_sparc_ShiftRA_imm(dbgi, block, lshift_node, shift_width);
ir_node *lshift_node = new_bd_sparc_Sll_imm(dbgi, block, op, shift_width);
ir_node *rshift_node = new_bd_sparc_Sra_imm(dbgi, block, lshift_node, shift_width);
return rshift_node;
}
......@@ -325,7 +325,7 @@ static ir_node *gen_Load(ir_node *node)
if (mode_is_float(mode))
panic("SPARC: no fp implementation yet");
new_load = new_bd_sparc_Load(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
new_load = new_bd_sparc_Ld(dbgi, block, new_ptr, new_mem, mode, NULL, 0, 0, false);
set_irn_pinned(new_load, get_irn_pinned(node));
return new_load;
......@@ -355,7 +355,7 @@ static ir_node *gen_Store(ir_node *node)
if (mode_is_float(mode))
panic("SPARC: no fp implementation yet");
new_store = new_bd_sparc_Store(dbgi, block, new_ptr, new_val, new_mem, mode, NULL, 0, 0, false);
new_store = new_bd_sparc_St(dbgi, block, new_ptr, new_val, new_mem, mode, NULL, 0, 0, false);
return new_store;
}
......@@ -453,7 +453,7 @@ static ir_node *gen_Abs(ir_node *node) {
new_op = be_transform_node(op);
mov = new_bd_sparc_Mov_reg(dbgi, block, new_op);
sra = new_bd_sparc_ShiftRA_imm(dbgi, block, mov, 31);
sra = new_bd_sparc_Sra_imm(dbgi, block, mov, 31);
xor = new_bd_sparc_Xor_reg(dbgi, block, new_op, sra);
sub = new_bd_sparc_Sub_reg(dbgi, block, sra, xor);
......@@ -522,17 +522,17 @@ static ir_node *gen_Xor(ir_node *node)
static ir_node *gen_Shl(ir_node *node)
{
return gen_helper_binop(node, MATCH_SIZE_NEUTRAL, new_bd_sparc_ShiftLL_reg, new_bd_sparc_ShiftLL_imm);
return gen_helper_binop(node, MATCH_SIZE_NEUTRAL, new_bd_sparc_Sll_reg, new_bd_sparc_Sll_imm);
}
static ir_node *gen_Shr(ir_node *node)
{
return gen_helper_binop(node, MATCH_SIZE_NEUTRAL, new_bd_sparc_ShiftLR_reg, new_bd_sparc_ShiftLR_imm);
return gen_helper_binop(node, MATCH_SIZE_NEUTRAL, new_bd_sparc_Slr_reg, new_bd_sparc_Slr_imm);
}
static ir_node *gen_Shra(ir_node *node)
{
return gen_helper_binop(node, MATCH_SIZE_NEUTRAL, new_bd_sparc_ShiftRA_reg, new_bd_sparc_ShiftRA_imm);
return gen_helper_binop(node, MATCH_SIZE_NEUTRAL, new_bd_sparc_Sra_reg, new_bd_sparc_Sra_imm);
}
/****** TRANSFORM GENERAL BACKEND NODES ********/
......@@ -595,7 +595,7 @@ static ir_node *gen_be_AddSP(ir_node *node)
ir_node *new_op;
/* SPARC stack grows in reverse direction */
new_op = new_bd_sparc_AddSP(dbgi, block, new_sp, new_sz, nomem);
new_op = new_bd_sparc_SubSP(dbgi, block, new_sp, new_sz, nomem);
return new_op;
}
......@@ -618,7 +618,7 @@ static ir_node *gen_be_SubSP(ir_node *node)
ir_node *new_op;
/* SPARC stack grows in reverse direction */
new_op = new_bd_sparc_SubSP(dbgi, block, new_sp, new_sz, nomem);
new_op = new_bd_sparc_AddSP(dbgi, block, new_sp, new_sz, nomem);
return new_op;
}
......@@ -731,7 +731,7 @@ static ir_node *gen_Cond(ir_node *node)
block = be_transform_node(get_nodes_block(node));
dbgi = get_irn_dbg_info(node);
flag_node = be_transform_node(get_Proj_pred(selector));
return new_bd_sparc_Branch(dbgi, block, flag_node, get_Proj_proj(selector));
return new_bd_sparc_BXX(dbgi, block, flag_node, get_Proj_proj(selector));
}
/**
......@@ -825,17 +825,17 @@ static ir_node *gen_Conv(ir_node *node)
if (mode_is_float(dst_mode)) {
// float -> float conv
if (src_bits > dst_bits) {
return new_bd_sparc_FpDToFpS(dbg, block, new_op, dst_mode);
return new_bd_sparc_FsTOd(dbg, block, new_op, dst_mode);
} else {
return new_bd_sparc_FpSToFpD(dbg, block, new_op, dst_mode);
return new_bd_sparc_FdTOs(dbg, block, new_op, dst_mode);
}
} else {
// float -> int conv
switch (dst_bits) {
case 32:
return new_bd_sparc_FpSToInt(dbg, block, new_op, dst_mode);
return new_bd_sparc_FsTOi(dbg, block, new_op, dst_mode);
case 64:
return new_bd_sparc_FpDToInt(dbg, block, new_op, dst_mode);
return new_bd_sparc_FdTOi(dbg, block, new_op, dst_mode);
default:
panic("quad FP not implemented");
}
......@@ -844,9 +844,9 @@ static ir_node *gen_Conv(ir_node *node)
// int -> float conv
switch (dst_bits) {
case 32:
return new_bd_sparc_IntToFpS(dbg, block, new_op, src_mode);
return new_bd_sparc_FiTOs(dbg, block, new_op, src_mode);
case 64:
return new_bd_sparc_IntToFpD(dbg, block, new_op, src_mode);
return new_bd_sparc_FiTOd(dbg, block, new_op, src_mode);
default:
panic("quad FP not implemented");
}
......@@ -944,19 +944,14 @@ static ir_node *gen_Proj_Load(ir_node *node)
/* renumber the proj */
switch (get_sparc_irn_opcode(new_load)) {
case iro_sparc_Load:
case iro_sparc_Ld:
/* handle all gp loads equal: they have the same proj numbers. */
if (proj == pn_Load_res) {
return new_rd_Proj(dbgi, new_load, mode_Iu, pn_sparc_Load_res);
return new_rd_Proj(dbgi, new_load, mode_Iu, pn_sparc_Ld_res);
} else if (proj == pn_Load_M) {
return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Load_M);
return new_rd_Proj(dbgi, new_load, mode_M, pn_sparc_Ld_M);
}
break;
/*
case iro_sparc_fpaLoad:
panic("FP not implemented yet");
break;
*/
break;
default:
panic("Unsupported Proj from Load");
}
......@@ -1114,7 +1109,7 @@ static ir_node *gen_Jmp(ir_node *node)
ir_node *new_block = be_transform_node(block);
dbg_info *dbgi = get_irn_dbg_info(node);
return new_bd_sparc_Jmp(dbgi, new_block);
return new_bd_sparc_Ba(dbgi, new_block);
}
/**
......
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