Commit a824d376 authored by Matthias Braun's avatar Matthias Braun
Browse files

- Part1 of backend reorganisation:

	Node flags and node registers are stored in a generic backend_info struct now
	instead of every part of the backend doing custom (and slow) stuff

[r23142]
parent 11b7b651
......@@ -205,9 +205,6 @@ static int TEMPLATE_dump_node(ir_node *n, FILE *F, dump_reason_t reason) {
if (attr->flags & arch_irn_flags_rematerializable) {
fprintf(F, " remat");
}
if (attr->flags & arch_irn_flags_ignore) {
fprintf(F, " ignore");
}
}
fprintf(F, " (%d)\n", attr->flags);
......
......@@ -112,49 +112,6 @@ static const arch_register_req_t *TEMPLATE_get_irn_reg_req(const ir_node *node,
return arch_no_register_req;
}
static void TEMPLATE_set_irn_reg(ir_node *irn, const arch_register_t *reg)
{
int pos = 0;
if (is_Proj(irn)) {
pos = TEMPLATE_translate_proj_pos(irn);
irn = skip_Proj(irn);
}
if (is_TEMPLATE_irn(irn)) {
const arch_register_t **slots;
slots = get_TEMPLATE_slots(irn);
slots[pos] = reg;
}
else {
/* here we set the registers for the Phi nodes */
TEMPLATE_set_firm_reg(irn, reg, cur_reg_set);
}
}
static const arch_register_t *TEMPLATE_get_irn_reg(const ir_node *irn)
{
int pos = 0;
const arch_register_t *reg = NULL;
if (is_Proj(irn)) {
pos = TEMPLATE_translate_proj_pos(irn);
irn = skip_Proj_const(irn);
}
if (is_TEMPLATE_irn(irn)) {
const arch_register_t * const *slots;
slots = get_TEMPLATE_slots_const(irn);
reg = slots[pos];
}
else {
reg = TEMPLATE_get_firm_reg(irn, cur_reg_set);
}
return reg;
}
static arch_irn_class_t TEMPLATE_classify(const ir_node *irn)
{
irn = skip_Proj_const(irn);
......@@ -166,20 +123,6 @@ static arch_irn_class_t TEMPLATE_classify(const ir_node *irn)
return 0;
}
static arch_irn_flags_t TEMPLATE_get_flags(const ir_node *irn)
{
irn = skip_Proj_const(irn);
if (is_TEMPLATE_irn(irn)) {
return get_TEMPLATE_flags(irn);
}
else if (is_Unknown(irn)) {
return arch_irn_flags_ignore;
}
return 0;
}
static ir_entity *TEMPLATE_get_frame_entity(const ir_node *node)
{
(void) node;
......@@ -215,10 +158,7 @@ static int TEMPLATE_get_sp_bias(const ir_node *irn)
static const arch_irn_ops_t TEMPLATE_irn_ops = {
TEMPLATE_get_irn_reg_req,
TEMPLATE_set_irn_reg,
TEMPLATE_get_irn_reg,
TEMPLATE_classify,
TEMPLATE_get_flags,
TEMPLATE_get_frame_entity,
TEMPLATE_set_frame_entity,
TEMPLATE_set_frame_offset,
......@@ -664,6 +604,7 @@ static int TEMPLATE_is_valid_clobber(const void *self, const char *clobber)
const arch_isa_if_t TEMPLATE_isa_if = {
TEMPLATE_init,
TEMPLATE_done,
NULL, /* handle intrinsics */
TEMPLATE_get_n_reg_class,
TEMPLATE_get_reg_class,
TEMPLATE_get_reg_class_for_mode,
......
......@@ -235,9 +235,6 @@ static int arm_dump_node(ir_node *n, FILE *F, dump_reason_t reason) {
if (attr->flags & arch_irn_flags_rematerializable) {
fprintf(F, " remat");
}
if (attr->flags & arch_irn_flags_ignore) {
fprintf(F, " ignore");
}
}
fprintf(F, " (%d)\n", attr->flags);
......
......@@ -10,99 +10,6 @@ $new_emit_syntax = 1;
# the number of additional opcodes you want to register
#$additional_opcodes = 0;
# The node description is done as a perl hash initializer with the
# following structure:
#
# %nodes = (
#
# <op-name> => {
# op_flags => "N|L|C|X|I|F|Y|H|c|K",
# irn_flags => "R|N|I|S"
# arity => "0|1|2|3 ... |variable|dynamic|any",
# state => "floats|pinned|mem_pinned|exc_pinned",
# args => [
# { type => "type 1", name => "name 1" },
# { type => "type 2", name => "name 2" },
# ...
# ],
# comment => "any comment for constructor",
# reg_req => { in => [ "reg_class|register" ], out => [ "reg_class|register|in_rX" ] },
# cmp_attr => "c source code for comparing node attributes",
# outs => { "out1", "out2" } # optional, creates pn_op_out1, ... consts
# ins => { "in1", "in2" } # optional, creates n_op_in1, ... consts
# mode => "mode_Iu" # optional, predefines the mode
# emit => "emit code with templates",
# attr => "attitional attribute arguments for constructor",
# init_attr => "emit attribute initialization template",
# rd_constructor => "c source code which constructs an ir_node"
# hash_func => "name of the hash function for this operation",
# latency => "latency of this operation (can be float)"
# attr_type => "name of the attribute struct",
# },
#
# ... # (all nodes you need to describe)
#
# ); # close the %nodes initializer
# op_flags: flags for the operation, OPTIONAL (default is "N")
# the op_flags correspond to the firm irop_flags:
# N irop_flag_none
# L irop_flag_labeled
# C irop_flag_commutative
# X irop_flag_cfopcode
# I irop_flag_ip_cfopcode
# F irop_flag_fragile
# Y irop_flag_forking
# H irop_flag_highlevel
# c irop_flag_constlike
# K irop_flag_keep
#
# irn_flags: special node flags, OPTIONAL (default is 0)
# following irn_flags are supported:
# R rematerializeable
# N not spillable
# I ignore for register allocation
# S modifies stack pointer
#
# state: state of the operation, OPTIONAL (default is "floats")
#
# arity: arity of the operation, MUST NOT BE OMITTED
#
# args: the OPTIONAL arguments of the node constructor (debug, irg and block
# are always the first 3 arguments and are always autmatically
# created)
# If this key is missing the following arguments will be created:
# for i = 1 .. arity: ir_node *op_i
# ir_mode *mode
#
# outs: if a node defines more than one output, the names of the projections
# nodes having outs having automatically the mode mode_T
# One can also annotate some flags for each out, additional to irn_flags.
# They are separated from name with a colon ':', and concatenated by pipe '|'
# Only I and S are available at the moment (same meaning as in irn_flags).
# example: [ "frame:I", "stack:I|S", "M" ]
#
# comment: OPTIONAL comment for the node constructor
#
# rd_constructor: for every operation there will be a
# new_rd_<arch>_<op-name> function with the arguments from above
# which creates the ir_node corresponding to the defined operation
# you can either put the complete source code of this function here
#
# This key is OPTIONAL. If omitted, the following constructor will
# be created:
# if (!op_<arch>_<op-name>) assert(0);
# for i = 1 to arity
# set in[i] = op_i
# done
# res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
# return res
#
# NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
#
# latency: the latency of the operation, default is 1
#
#
# Modes
#
......@@ -232,8 +139,7 @@ $default_copy_attr = "arm_copy_attr";
Unknown_GP => {
state => "pinned",
op_flags => "c",
irn_flags => "I",
reg_req => { out => [ "gp_UKNWN" ] },
reg_req => { out => [ "gp_UKNWN:I" ] },
emit => "",
mode => $mode_gp,
},
......@@ -241,8 +147,7 @@ Unknown_GP => {
Unknown_FPA => {
state => "pinned",
op_flags => "c",
irn_flags => "I",
reg_req => { out => [ "fpa_UKNWN" ] },
reg_req => { out => [ "fpa_UKNWN:I" ] },
emit => "",
mode => $mode_fpa,
},
......@@ -1029,21 +934,19 @@ fpaDbl2GP => {
},
AddSP => {
irn_flags => "I",
comment => "construct Add to stack pointer",
reg_req => { in => [ "sp", "gp", "none" ], out => [ "in_r1", "none" ] },
reg_req => { in => [ "sp", "gp", "none" ], out => [ "sp:I|S", "none" ] },
emit => '. add %D0, %S0, %S1',
outs => [ "stack:I|S", "M" ],
outs => [ "stack", "M" ],
},
SubSPandCopy => {
#irn_flags => "I",
comment => "construct Sub from stack pointer and copy to Register",
reg_req => { in => [ "sp", "gp", "none" ], out => [ "in_r1", "gp", "none" ] },
reg_req => { in => [ "sp", "gp", "none" ], out => [ "sp:I|S", "gp", "none" ] },
ins => [ "stack", "size", "mem" ],
emit => ". sub %D0, %S0, %S1\n".
". mov sp, %D1",
outs => [ "stack:I|S", "addr", "M" ],
outs => [ "stack", "addr", "M" ],
},
LdTls => {
......
......@@ -130,58 +130,6 @@ static const arch_register_req_t *arm_get_irn_reg_req(const ir_node *node,
return arch_no_register_req;
}
static void arm_set_irn_reg(ir_node *irn, const arch_register_t *reg)
{
int pos = 0;
if (get_irn_mode(irn) == mode_X) {
return;
}
if (is_Proj(irn)) {
pos = get_Proj_proj(irn);
irn = skip_Proj(irn);
}
if (is_arm_irn(irn)) {
const arch_register_t **slots;
slots = get_arm_slots(irn);
slots[pos] = reg;
}
else {
/* here we set the registers for the Phi nodes */
arm_set_firm_reg(irn, reg, cur_reg_set);
}
}
static const arch_register_t *arm_get_irn_reg(const ir_node *irn)
{
int pos = 0;
const arch_register_t *reg = NULL;
if (is_Proj(irn)) {
if (get_irn_mode(irn) == mode_X) {
return NULL;
}
pos = get_Proj_proj(irn);
irn = skip_Proj_const(irn);
}
if (is_arm_irn(irn)) {
const arch_register_t **slots;
slots = get_arm_slots(irn);
reg = slots[pos];
}
else {
reg = arm_get_firm_reg(irn, cur_reg_set);
}
return reg;
}
static arch_irn_class_t arm_classify(const ir_node *irn)
{
irn = skip_Proj_const(irn);
......@@ -193,29 +141,6 @@ static arch_irn_class_t arm_classify(const ir_node *irn)
return 0;
}
static arch_irn_flags_t arm_get_flags(const ir_node *irn)
{
arch_irn_flags_t flags = arch_irn_flags_none;
if(is_Unknown(irn)) {
return arch_irn_flags_ignore;
}
if (is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
ir_node *pred = get_Proj_pred(irn);
if (is_arm_irn(pred)) {
flags = get_arm_out_flags(pred, get_Proj_proj(irn));
}
irn = pred;
}
if (is_arm_irn(irn)) {
flags |= get_arm_flags(irn);
}
return flags;
}
static ir_entity *arm_get_frame_entity(const ir_node *irn) {
/* we do NOT transform be_Spill or be_Reload nodes, so we never
have frame access using ARM nodes. */
......@@ -250,10 +175,7 @@ static int arm_get_sp_bias(const ir_node *irn)
static const arch_irn_ops_t arm_irn_ops = {
arm_get_irn_reg_req,
arm_set_irn_reg,
arm_get_irn_reg,
arm_classify,
arm_get_flags,
arm_get_frame_entity,
arm_set_frame_entity,
arm_set_stack_bias,
......@@ -908,8 +830,7 @@ static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *
block = get_irg_start_block(irg);
ip = be_new_Copy(gp, irg, block, sp);
arch_set_irn_register(ip, &arm_gp_regs[REG_R12]);
be_set_constr_single_reg(ip, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
be_set_constr_single_reg_out(ip, 0, &arm_gp_regs[REG_R12], arch_register_req_type_produces_sp);
store = new_rd_arm_StoreStackM4Inc(NULL, irg, block, sp, fp, ip, lr, pc, *mem);
......@@ -918,15 +839,13 @@ static const arch_register_t *arm_abi_prologue(void *self, ir_node **mem, pmap *
*mem = new_r_Proj(irg, block, store, mode_M, pn_arm_StoreStackM4Inc_M);
keep = be_new_CopyKeep_single(gp, irg, block, ip, sp, get_irn_mode(ip));
be_node_set_reg_class(keep, 1, gp);
arch_set_irn_register(keep, &arm_gp_regs[REG_R12]);
be_set_constr_single_reg(keep, BE_OUT_POS(0), &arm_gp_regs[REG_R12] );
be_node_set_reg_class_in(keep, 1, gp);
be_set_constr_single_reg_out(keep, 0, &arm_gp_regs[REG_R12], arch_register_req_type_produces_sp);
fp = new_rd_arm_Sub_i(NULL, irg, block, keep, get_irn_mode(fp), 4);
arch_set_irn_register(fp, env->arch_env->bp);
fp = be_new_Copy(gp, irg, block, fp); // XXX Gammelfix: only be_ nodes can have the ignore flag set
arch_set_irn_register(fp, env->arch_env->bp);
be_node_set_flags(fp, BE_OUT_POS(0), arch_irn_flags_ignore);
fp = be_new_Copy(gp, irg, block, fp); // XXX Gammelfix: only be_ have custom register requirements
be_set_constr_single_reg_out(fp, 0, env->arch_env->bp, 0);
be_abi_reg_map_set(reg_map, env->arch_env->bp, fp);
be_abi_reg_map_set(reg_map, &arm_gp_regs[REG_R12], keep);
......@@ -952,14 +871,10 @@ static void arm_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_m
curr_sp = be_new_IncSP(env->arch_env->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
curr_lr = be_new_CopyKeep_single(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr, curr_sp, get_irn_mode(curr_lr));
be_node_set_reg_class(curr_lr, 1, &arm_reg_classes[CLASS_arm_gp]);
arch_set_irn_register(curr_lr, &arm_gp_regs[REG_LR]);
be_set_constr_single_reg(curr_lr, BE_OUT_POS(0), &arm_gp_regs[REG_LR] );
be_set_constr_single_reg_out(curr_lr, 0, &arm_gp_regs[REG_LR], 0);
curr_pc = be_new_Copy(&arm_reg_classes[CLASS_arm_gp], env->irg, bl, curr_lr );
arch_set_irn_register(curr_pc, &arm_gp_regs[REG_PC]);
be_set_constr_single_reg(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC] );
be_node_set_flags(curr_pc, BE_OUT_POS(0), arch_irn_flags_ignore);
be_set_constr_single_reg_out(curr_pc, BE_OUT_POS(0), &arm_gp_regs[REG_PC], 0);
} else {
ir_node *sub12_node;
ir_node *load_node;
......@@ -1243,6 +1158,7 @@ static const lc_opt_table_entry_t arm_options[] = {
const arch_isa_if_t arm_isa_if = {
arm_init,
arm_done,
NULL, /* handle_intrinsics */
arm_get_n_reg_class,
arm_get_reg_class,
arm_get_reg_class_for_mode,
......
......@@ -665,10 +665,9 @@ static ir_node *adjust_call(be_abi_irg_t *env, ir_node *irn, ir_node *curr_sp)
/* create new stack pointer */
curr_sp = new_r_Proj(irg, bl, low_call, get_irn_mode(curr_sp),
pn_be_Call_sp);
be_set_constr_single_reg(low_call, BE_OUT_POS(pn_be_Call_sp), sp);
be_set_constr_single_reg_out(low_call, pn_be_Call_sp, sp,
arch_register_req_type_ignore | arch_register_req_type_produces_sp);
arch_set_irn_register(curr_sp, sp);
be_node_set_flags(low_call, BE_OUT_POS(pn_be_Call_sp),
arch_irn_flags_ignore | arch_irn_flags_modify_sp);
for(i = 0; i < n_res; ++i) {
int pn;
......@@ -704,7 +703,7 @@ static ir_node *adjust_call(be_abi_irg_t *env, ir_node *irn, ir_node *curr_sp)
Set the register class of the call address to
the backend provided class (default: stack pointer class)
*/
be_node_set_reg_class(low_call, be_pos_Call_ptr, call->cls_addr);
be_node_set_reg_class_in(low_call, be_pos_Call_ptr, call->cls_addr);
DBG((env->dbg, LEVEL_3, "\tcreated backend call %+F\n", low_call));
......@@ -714,7 +713,8 @@ static ir_node *adjust_call(be_abi_irg_t *env, ir_node *irn, ir_node *curr_sp)
be_abi_call_arg_t *arg = get_call_arg(call, 0, index);
assert(arg->reg != NULL);
be_set_constr_single_reg(low_call, be_pos_Call_first_arg + i, arg->reg);
be_set_constr_single_reg_in(low_call, be_pos_Call_first_arg + i,
arg->reg, 0);
}
/* Set the register constraints of the results. */
......@@ -724,7 +724,7 @@ static ir_node *adjust_call(be_abi_irg_t *env, ir_node *irn, ir_node *curr_sp)
int pn = get_Proj_proj(proj);
assert(arg->in_reg);
be_set_constr_single_reg(low_call, BE_OUT_POS(pn), arg->reg);
be_set_constr_single_reg_out(low_call, pn, arg->reg, 0);
arch_set_irn_register(proj, arg->reg);
}
obstack_free(obst, in);
......@@ -755,15 +755,9 @@ static ir_node *adjust_call(be_abi_irg_t *env, ir_node *irn, ir_node *curr_sp)
curr_res_proj);
/* memorize the register in the link field. we need afterwards to set the register class of the keep correctly. */
be_set_constr_single_reg(low_call, BE_OUT_POS(curr_res_proj), reg);
be_set_constr_single_reg_out(low_call, curr_res_proj, reg, 0);
arch_set_irn_register(proj, reg);
/* a call can produce ignore registers, in this case set the flag and register for the Proj */
if (arch_register_type_is(reg, ignore)) {
be_node_set_flags(low_call, BE_OUT_POS(curr_res_proj),
arch_irn_flags_ignore);
}
set_irn_link(proj, (void*) reg);
obstack_ptr_grow(obst, proj);
curr_res_proj++;
......@@ -782,7 +776,7 @@ static ir_node *adjust_call(be_abi_irg_t *env, ir_node *irn, ir_node *curr_sp)
keep = be_new_Keep(NULL, irg, bl, n, in);
for (i = 0; i < n; ++i) {
const arch_register_t *reg = get_irn_link(in[i]);
be_node_set_reg_class(keep, i, reg->reg_class);
be_node_set_reg_class_in(keep, i, reg->reg_class);
}
obstack_free(obst, in);
}
......@@ -1246,50 +1240,6 @@ static ir_type *compute_arg_type(be_abi_irg_t *env, be_abi_call_t *call, ir_type
return res;
}
#if 0
static void create_register_perms(const arch_isa_t *isa, ir_graph *irg, ir_node *bl, pmap *regs)
{
int i, j, n;
struct obstack obst;
obstack_init(&obst);
/* Create a Perm after the RegParams node to delimit it. */
for (i = 0, n = arch_isa_get_n_reg_class(isa); i < n; ++i) {
const arch_register_class_t *cls = arch_isa_get_reg_class(isa, i);
ir_node *perm;
ir_node **in;
int n_regs;
for (n_regs = 0, j = 0; j < cls->n_regs; ++j) {
const arch_register_t *reg = &cls->regs[j];
ir_node *irn = pmap_get(regs, (void *) reg);
if(irn && !arch_register_type_is(reg, ignore)) {
n_regs++;
obstack_ptr_grow(&obst, irn);
set_irn_link(irn, (void *) reg);
}
}
obstack_ptr_grow(&obst, NULL);
in = obstack_finish(&obst);
if (n_regs > 0) {
perm = be_new_Perm(cls, irg, bl, n_regs, in);
for (j = 0; j < n_regs; ++j) {
ir_node *arg = in[j];
arch_register_t *reg = get_irn_link(arg);
pmap_insert(regs, reg, arg);
be_set_constr_single_reg(perm, BE_OUT_POS(j), reg);
}
}
obstack_free(&obst, in);
}
obstack_free(&obst, NULL);
}
#endif
typedef struct {
const arch_register_t *reg;
ir_node *irn;
......@@ -1350,28 +1300,28 @@ static ir_node *create_barrier(be_abi_irg_t *env, ir_node *bl, ir_node **mem, pm
obstack_free(&env->obst, in);
for(n = 0; n < n_regs; ++n) {
const arch_register_t *reg = rm[n].reg;
int flags = 0;
int pos = BE_OUT_POS(n);
ir_node *proj;
ir_node *pred = rm[n].irn;
const arch_register_t *reg = rm[n].reg;
arch_register_type_t add_type = 0;
ir_node *proj;
/* stupid workaround for now... as not all nodes report register
* requirements. */
if (!is_Phi(pred)) {
const arch_register_req_t *ireq = arch_get_register_req_out(pred);
if (ireq->type & arch_register_req_type_ignore)
add_type |= arch_register_req_type_ignore;
if (ireq->type & arch_register_req_type_produces_sp)
add_type |= arch_register_req_type_produces_sp;
}
proj = new_r_Proj(irg, bl, irn, get_irn_mode(rm[n].irn), n);
be_node_set_reg_class(irn, n, reg->reg_class);
proj = new_r_Proj(irg, bl, irn, get_irn_mode(pred), n);
be_node_set_reg_class_in(irn, n, reg->reg_class);
if (in_req)
be_set_constr_single_reg(irn, n, reg);
be_set_constr_single_reg(irn, pos, reg);
be_node_set_reg_class(irn, pos, reg->reg_class);
be_set_constr_single_reg_in(irn, n, reg, 0);
be_set_constr_single_reg_out(irn, n, reg, add_type);
arch_set_irn_register(proj, reg);
/* if the proj projects a ignore register or a node which is set to ignore, propagate this property. */
if (arch_register_type_is(reg, ignore) || arch_irn_is(in[n], ignore))
flags |= arch_irn_flags_ignore;
if (arch_irn_is(in[n], modify_sp))
flags |= arch_irn_flags_modify_sp;
be_node_set_flags(irn, pos, flags);
pmap_insert(regs, (void *) reg, proj);
}
......@@ -1490,9 +1440,12 @@ static ir_node *create_be_return(be_abi_irg_t *env, ir_node *irn, ir_node *bl,
ret = be_new_Return(dbgi, env->birg->irg, bl, n_res, pop, n, in);
/* Set the register classes of the return's parameter accordingly. */
for (i = 0; i < n; ++i)
if (regs[i])
be_node_set_reg_class(ret, i, regs[i]->reg_class);
for (i = 0; i < n; ++i) {
if (regs[i] == NULL)
continue;
be_node_set_reg_class_in(ret, i, regs[i]->reg_class);
}
/* Free the space of the Epilog's in array and the register <-> proj map. */
obstack_free(&env->obst, in);
......@@ -1824,33 +1777,22 @@ static void modify_irg(be_abi_irg_t *env)
rm = reg_map_to_arr(&env->obst, env->regs);
for (i = 0, n = pmap_count(env->regs); i < n; ++i) {
arch_register_t *reg = (void *) rm[i].reg;
ir_mode *mode = reg->reg_class->mode;
long nr = i;
int pos = BE_OUT_POS((int) nr);
int flags = 0;
arch_register_t *reg = (void *) rm[i].reg;
ir_mode *mode = reg->reg_class->mode;
long nr = i;
arch_register_req_type_t add_type = 0;
ir_node *proj;
ir_node *proj;
if (reg == sp)
add_type |= arch_register_req_type_produces_sp | arch_register_req_type_ignore;
assert(nr >= 0);
bitset_set(used_proj_nr, nr);
proj = new_r_Proj(irg, reg_params_bl, env->reg_params, mode, nr);
pmap_insert(env->regs, (void *) reg, proj);
be_set_constr_single_reg(env->reg_params, pos, reg);
be_set_constr_single_reg_out(env->reg_params, nr, reg, add_type);
arch_set_irn_register(proj, reg);
/*
* If the register is an ignore register,
* The Proj for that register shall also be ignored during register allocation.
*/
if (arch_register_type_is(reg, ignore))
flags |= arch_irn_flags_ignore;