ia32: Rename nodes to match the spelling of the assembler.

Prefetch0 -> PrefetchT0
Prefetch1 -> PrefetchT1
Prefetch2 -> PrefetchT2
Ucomi     -> Ucomis
xAdd      -> Adds
xAnd      -> Andp
xAndNot   -> Andnp
xDiv      -> Divs
xMax      -> Maxs
xMin      -> Mins
xMovd     -> Movd
xMul      -> Muls
xOr       -> Orp
xPslld    -> Pslld
xPsllq    -> Psllq
xPsrld    -> Psrld
xSub      -> Subs
xXor      -> Xorp

ir/be/ia32/ia32_finish.c

@@ -52,12 +52,12 @@ static bool ia32_transform_sub_to_neg_add(ir_node *const irn,
 
 	/* generate the neg src2 */
 	ir_node *res;
-	if (is_ia32_xSub(irn)) {
+	if (is_ia32_Subs(irn)) {
 		x86_insn_size_t const size = get_ia32_attr_const(irn)->size;
 		assert(get_irn_mode(irn) != mode_T);
 
 		ir_node *const noreg_fp = ia32_new_NoReg_xmm(irg);
-		res = new_bd_ia32_xXor(dbgi, block, noreg, noreg, nomem, in2, noreg_fp,
+		res = new_bd_ia32_Xorp(dbgi, block, noreg, noreg, nomem, in2, noreg_fp,
 		                       size);
 		ir_entity *entity = ia32_gen_fp_known_const(size == X86_SIZE_32
 		                                            ? ia32_SSIGN : ia32_DSIGN);
@@ -71,7 +71,7 @@ static bool ia32_transform_sub_to_neg_add(ir_node *const irn,
 		sched_add_before(irn, res);
 
 		/* generate the add */
-		res = new_bd_ia32_xAdd(dbgi, block, noreg, noreg, nomem, res, in1,
+		res = new_bd_ia32_Adds(dbgi, block, noreg, noreg, nomem, res, in1,
 		                       size);
 	} else {
 		ir_node *flags_proj  = NULL;
@@ -216,7 +216,7 @@ static bool ia32_handle_2addr(ir_node *const node, arch_register_req_t const *co
 		}
 	} else if (is_ia32_ShlD(node)) {
 		return ia32_transform_ShlD_to_ShrD_imm(node, reg);
-	} else if (is_ia32_Sub(node) || is_ia32_Sbb(node) || is_ia32_xSub(node)) {
+	} else if (is_ia32_Sub(node) || is_ia32_Sbb(node) || is_ia32_Subs(node)) {
 		return ia32_transform_sub_to_neg_add(node, reg);
 	}
 	return false;

ir/be/ia32/ia32_spec.pl

@@ -1335,19 +1335,19 @@ Inport => {
 },
 
 # Intel style prefetching
-Prefetch0 => {
+PrefetchT0 => {
 	template => $prefetchop,
 	latency  => 0,
 	emit     => "prefetcht0 %AM",
 },
 
-Prefetch1 => {
+PrefetchT1 => {
 	template => $prefetchop,
 	latency  => 0,
 	emit     => "prefetcht1 %AM",
 },
 
-Prefetch2 => {
+PrefetchT2 => {
 	template => $prefetchop,
 	latency  => 0,
 	emit     => "prefetcht2 %AM",
@@ -1399,28 +1399,28 @@ xAllOnes => {
 },
 
 # integer shift left, dword
-xPslld => {
+Pslld => {
 	template => $xshiftop,
 	emit     => "pslld %S1, %D0",
 	latency  => 3,
 },
 
 # integer shift left, qword
-xPsllq => {
+Psllq => {
 	template => $xshiftop,
 	emit     => "psllq %S1, %D0",
 	latency  => 3,
 },
 
 # integer shift right, dword
-xPsrld => {
+Psrld => {
 	template => $xshiftop,
 	emit     => "psrld %S1, %D0",
 	latency  => 1,
 },
 
 # mov from integer to SSE register
-xMovd  => {
+Movd  => {
 	irn_flags => [ "rematerializable" ],
 	in_reqs   => [ "gp" ],
 	out_reqs  => [ "xmm" ],
@@ -1429,55 +1429,55 @@ xMovd  => {
 	latency   => 1,
 },
 
-xAdd => {
+Adds => {
 	template => $xbinop_commutative,
 	emit     => "adds%FX %B",
 	latency  => 4,
 },
 
-xMul => {
+Muls => {
 	template => $xbinop_commutative,
 	emit     => "muls%FX %B",
 	latency  => 4,
 },
 
-xMax => {
+Maxs => {
 	template => $xbinop_commutative,
 	emit     => "maxs%FX %B",
 	latency  => 2,
 },
 
-xMin => {
+Mins => {
 	template => $xbinop_commutative,
 	emit     => "mins%FX %B",
 	latency  => 2,
 },
 
-xAnd => {
+Andp => {
 	template => $xbinop_commutative,
 	emit     => "andp%FX %B",
 	latency  => 3,
 },
 
-xOr => {
+Orp => {
 	template => $xbinop_commutative,
 	emit     => "orp%FX %B",
 	latency  => 3,
 },
 
-xXor => {
+Xorp => {
 	template => $xbinop_commutative,
 	emit     => "xorp%FX %B",
 	latency  => 3,
 },
 
-xAndNot => {
+Andnp => {
 	template => $xbinop,
 	emit     => "andnp%FX %B",
 	latency  => 3,
 },
 
-xSub => {
+Subs => {
 	irn_flags => [ "rematerializable" ],
 	state     => "exc_pinned",
 	in_reqs   => [ "gp", "gp", "mem", "xmm", "xmm" ],
@@ -1491,7 +1491,7 @@ xSub => {
 	mode      => "first"
 },
 
-xDiv => {
+Divs => {
 	template => $xbinop,
 	am       => "source,binary",
 	emit     => "divs%FX %B",
@@ -1499,7 +1499,7 @@ xDiv => {
 	mode     => "mode_T"
 },
 
-Ucomi => {
+Ucomis => {
 	irn_flags => [ "modify_flags", "rematerializable" ],
 	state     => "exc_pinned",
 	in_reqs   => [ "gp", "gp", "mem", "xmm", "xmm" ],

ir/be/ia32/ia32_transform.c

@@ -362,7 +362,7 @@ static ir_node *gen_Const(ir_node *node)
 					.offset = be_get_tv_bits32(tv, 0),
 				};
 				ir_node *cnst = new_bd_ia32_Const(dbgi, block, &imm);
-				res = new_bd_ia32_xMovd(dbgi, block, cnst);
+				res = new_bd_ia32_Movd(dbgi, block, cnst);
 			} else {
 #ifdef CONSTRUCT_SSE_CONST
 				if (mode == ia32_mode_float64 && be_get_tv_bits32(tv, 0) == 0) {
@@ -1458,7 +1458,7 @@ static ir_node *gen_Add(ir_node *node)
 
 	if (mode_is_float(mode)) {
 		if (ia32_cg_config.use_sse2)
-			return gen_binop(node, op1, op2, new_bd_ia32_xAdd,
+			return gen_binop(node, op1, op2, new_bd_ia32_Adds,
 			                 match_commutative | match_am);
 		else
 			return gen_binop_x87_float(node, op1, op2, new_bd_ia32_fadd);
@@ -1529,7 +1529,7 @@ static ir_node *gen_Mul(ir_node *node)
 
 	if (mode_is_float(mode)) {
 		if (ia32_cg_config.use_sse2)
-			return gen_binop(node, op1, op2, new_bd_ia32_xMul,
+			return gen_binop(node, op1, op2, new_bd_ia32_Muls,
 			                 match_commutative | match_am);
 		else
 			return gen_binop_x87_float(node, op1, op2, new_bd_ia32_fmul);
@@ -1658,7 +1658,7 @@ static ir_node *gen_Sub(ir_node *node)
 
 	if (mode_is_float(mode)) {
 		if (ia32_cg_config.use_sse2)
-			return gen_binop(node, op1, op2, new_bd_ia32_xSub, match_am);
+			return gen_binop(node, op1, op2, new_bd_ia32_Subs, match_am);
 		else
 			return gen_binop_x87_float(node, op1, op2, new_bd_ia32_fsub);
 	}
@@ -1812,7 +1812,7 @@ static ir_node *gen_Div(ir_node *node)
 	ir_mode *const mode = get_Div_resmode(node);
 	if (mode_is_float(mode)) {
 		if (ia32_cg_config.use_sse2) {
-			return gen_binop(node, op1, op2, new_bd_ia32_xDiv, match_am);
+			return gen_binop(node, op1, op2, new_bd_ia32_Divs, match_am);
 		} else {
 			return gen_binop_x87_float(node, op1, op2, new_bd_ia32_fdiv);
 		}
@@ -1930,7 +1930,7 @@ static ir_node *gen_Minus(ir_node *node)
 			ir_node        *const noreg_xmm = ia32_new_NoReg_xmm(irg);
 			ir_node        *const base      = get_global_base(irg);
 			x86_insn_size_t const size      = x86_size_from_mode(mode);
-			ir_node        *const new_node  = new_bd_ia32_xXor(dbgi, block, base, noreg_GP, nomem, new_op, noreg_xmm, size);
+			ir_node        *const new_node  = new_bd_ia32_Xorp(dbgi, block, base, noreg_GP, nomem, new_op, noreg_xmm, size);
 
 			ir_entity      *const ent
 				= ia32_gen_fp_known_const(size == X86_SIZE_32 ? ia32_SSIGN
@@ -1997,7 +1997,7 @@ static ir_node *create_float_abs(dbg_info *const dbgi, ir_node *const new_block,
 		ir_node        *const noreg_fp = ia32_new_NoReg_xmm(irg);
 		ir_node        *const base     = get_global_base(irg);
 		x86_insn_size_t const size     = x86_size_from_mode(mode);
-		new_node = new_bd_ia32_xAnd(dbgi, new_block, base, noreg_GP, nomem,
+		new_node = new_bd_ia32_Andp(dbgi, new_block, base, noreg_GP, nomem,
 		                            new_op, noreg_fp, size);
 
 		ir_entity *ent = ia32_gen_fp_known_const(size == X86_SIZE_32
@@ -2898,9 +2898,7 @@ static ir_node *create_Ucomi(ir_node *node)
 	x86_address_t *addr = &am.addr;
 	ir_node  *new_block = be_transform_node(src_block);
 	dbg_info *dbgi      = get_irn_dbg_info(node);
-	ir_node  *new_node  = new_bd_ia32_Ucomi(dbgi, new_block, addr->base,
-	                                        addr->index, addr->mem, am.new_op1,
-	                                        am.new_op2, am.ins_permuted);
+	ir_node  *new_node  = new_bd_ia32_Ucomis(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted);
 	set_am_attributes(new_node, &am);
 	new_node = fix_mem_proj(new_node, &am);
 	return new_node;
@@ -3403,21 +3401,21 @@ static ir_node *gen_Mux(ir_node *node)
 			if (relation == ir_relation_less || relation == ir_relation_less_equal) {
 				if (cmp_left == mux_true && cmp_right == mux_false) {
 					/* Mux(a <= b, a, b) => MIN */
-					return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin,
+					return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_Mins,
 			                 match_commutative | match_am | match_two_users);
 				} else if (cmp_left == mux_false && cmp_right == mux_true) {
 					/* Mux(a <= b, b, a) => MAX */
-					return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax,
+					return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_Maxs,
 			                 match_commutative | match_am | match_two_users);
 				}
 			} else if (relation == ir_relation_greater || relation == ir_relation_greater_equal) {
 				if (cmp_left == mux_true && cmp_right == mux_false) {
 					/* Mux(a >= b, a, b) => MAX */
-					return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax,
+					return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_Maxs,
 			                 match_commutative | match_am | match_two_users);
 				} else if (cmp_left == mux_false && cmp_right == mux_true) {
 					/* Mux(a >= b, b, a) => MIN */
-					return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin,
+					return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_Mins,
 			                 match_commutative | match_am | match_two_users);
 				}
 			}
@@ -4655,8 +4653,8 @@ static ir_node *gen_Proj_Div(ir_node *node)
 	case pn_Div_M:
 		if (is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)) {
 			return be_new_Proj(new_pred, pn_ia32_Div_M);
-		} else if (is_ia32_xDiv(new_pred)) {
-			return be_new_Proj(new_pred, pn_ia32_xDiv_M);
+		} else if (is_ia32_Divs(new_pred)) {
+			return be_new_Proj(new_pred, pn_ia32_Divs_M);
 		} else if (is_ia32_fdiv(new_pred)) {
 			return be_new_Proj(new_pred, pn_ia32_fdiv_M);
 		} else {
@@ -4665,8 +4663,8 @@ static ir_node *gen_Proj_Div(ir_node *node)
 	case pn_Div_res:
 		if (is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)) {
 			return be_new_Proj(new_pred, pn_ia32_Div_div_res);
-		} else if (is_ia32_xDiv(new_pred)) {
-			return be_new_Proj(new_pred, pn_ia32_xDiv_res);
+		} else if (is_ia32_Divs(new_pred)) {
+			return be_new_Proj(new_pred, pn_ia32_Divs_res);
 		} else if (is_ia32_fdiv(new_pred)) {
 			return be_new_Proj(new_pred, pn_ia32_fdiv_res);
 		} else {
@@ -5058,13 +5056,13 @@ static ir_node *gen_prefetch(ir_node *node)
 			new_node = new_bd_ia32_PrefetchNTA(dbgi, block, base, idx, mem);
 			break;
 		case 1:
-			new_node = new_bd_ia32_Prefetch2(dbgi, block, base, idx, mem);
+			new_node = new_bd_ia32_PrefetchT2(dbgi, block, base, idx, mem);
 			break;
 		case 2:
-			new_node = new_bd_ia32_Prefetch1(dbgi, block, base, idx, mem);
+			new_node = new_bd_ia32_PrefetchT1(dbgi, block, base, idx, mem);
 			break;
 		default:
-			new_node = new_bd_ia32_Prefetch0(dbgi, block, base, idx, mem);
+			new_node = new_bd_ia32_PrefetchT0(dbgi, block, base, idx, mem);
 			break;
 		}
 	} else {