Commit ad8a59ef authored by Matthias Braun's avatar Matthias Braun
Browse files

- Use a default node compare attribute function for all nodes, except the ones

  where CSE is explicitely forbidden. This fixes some bugs where a cmp
  function was missing.
- Don't make all the nodes mode_T by default. They keep their normal mode
  node and only get set to mode_T is we actually use am_Dest
- get rid of src_mode and tgt_mode node attribute, you can get the modes
  by looking at the conv output mode and the arguments mode. This fixes
  some bugs where the src_mode and tgt_mode attributes were wrong
- cleaned up and fixed some bugs in addressmode optimisation
parent 9067a452
......@@ -117,7 +117,7 @@ static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_re
ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
if (is_Block(irn) || mode == mode_M || mode == mode_X) {
if (is_Block(irn) || mode == mode_X) {
DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
return NULL;
}
......@@ -130,6 +130,9 @@ static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_re
DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
if (is_Proj(irn)) {
if(mode == mode_M)
return NULL;
if(pos >= 0) {
DBG((mod, LEVEL_1, "ignoring request IN requirements for node %+F\n", irn));
return NULL;
......@@ -305,12 +308,9 @@ static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent
}
static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
char buf[64];
const ia32_irn_ops_t *ops = self;
if (get_ia32_frame_ent(irn)) {
ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
if(is_ia32_Pop(irn)) {
int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
if (omit_fp) {
......@@ -323,14 +323,17 @@ static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
snprintf(buf, sizeof(buf), "%d", bias);
if (get_ia32_op_type(irn) == ia32_Normal) {
// Matze: When does this case happen?
char buf[64];
snprintf(buf, sizeof(buf), "%d", bias);
set_ia32_cnst(irn, buf);
} else {
add_ia32_am_offs(irn, buf);
ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
am_flav |= ia32_O;
set_ia32_am_flavour(irn, am_flav);
add_ia32_am_offs_int(irn, bias);
}
}
}
......@@ -340,9 +343,9 @@ static int ia32_get_sp_bias(const void *self, const ir_node *irn) {
long proj = get_Proj_proj(irn);
ir_node *pred = get_Proj_pred(irn);
if (proj == pn_ia32_Push_stack && is_ia32_Push(pred))
if (is_ia32_Push(pred) && proj == pn_ia32_Push_stack)
return 4;
if (proj == pn_ia32_Pop_stack && is_ia32_Pop(pred))
if (is_ia32_Pop(pred) && proj == pn_ia32_Pop_stack)
return -4;
}
......@@ -599,8 +602,9 @@ static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
ir_graph *irg;
ir_mode *mode;
ir_mode *irn_mode;
ir_node *block, *noreg, *nomem;
int pnc;
dbg_info *dbg;
/* we cannot invert non-ia32 irns */
if (! is_ia32_irn(irn))
......@@ -614,24 +618,25 @@ static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, in
if (get_ia32_op_type(irn) != ia32_Normal)
return NULL;
irg = get_irn_irg(irn);
block = get_nodes_block(irn);
mode = get_ia32_res_mode(irn);
noreg = get_irn_n(irn, 0);
nomem = new_r_NoMem(irg);
irg = get_irn_irg(irn);
block = get_nodes_block(irn);
mode = get_ia32_res_mode(irn);
irn_mode = get_irn_mode(irn);
noreg = get_irn_n(irn, 0);
nomem = new_r_NoMem(irg);
dbg = get_irn_dbg_info(irn);
/* initialize structure */
inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
inverse->costs = 0;
inverse->n = 2;
inverse->n = 1;
switch (get_ia32_irn_opcode(irn)) {
case iro_ia32_Add:
if (get_ia32_immop_type(irn) == ia32_ImmConst) {
/* we have an add with a const here */
/* invers == add with negated const */
inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
pnc = pn_ia32_Add_res;
inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem, irn_mode);
inverse->costs += 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
......@@ -640,8 +645,7 @@ static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, in
else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
/* we have an add with a symconst here */
/* invers == sub with const */
inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
pnc = pn_ia32_Sub_res;
inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem, irn_mode);
inverse->costs += 2;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
......@@ -650,8 +654,7 @@ static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, in
ir_node *proj = ia32_get_res_proj(irn);
assert(proj);
inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, i ^ 1), nomem);
pnc = pn_ia32_Sub_res;
inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, proj, get_irn_n(irn, i ^ 1), nomem, irn_mode);
inverse->costs += 2;
}
break;
......@@ -659,8 +662,7 @@ static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, in
if (get_ia32_immop_type(irn) != ia32_ImmNone) {
/* we have a sub with a const/symconst here */
/* invers == add with this const */
inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
pnc = pn_ia32_Add_res;
inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem, irn_mode);
inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
......@@ -670,27 +672,24 @@ static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, in
assert(proj);
if (i == 2) {
inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, 3), nomem);
inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, proj, get_irn_n(irn, 3), nomem, irn_mode);
}
else {
inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, 2), proj, nomem);
inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, 2), proj, nomem, irn_mode);
}
pnc = pn_ia32_Sub_res;
inverse->costs += 1;
}
break;
case iro_ia32_Eor:
if (get_ia32_immop_type(irn) != ia32_ImmNone) {
/* xor with const: inverse = xor */
inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
pnc = pn_ia32_Eor_res;
inverse->nodes[0] = new_rd_ia32_Eor(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem, irn_mode);
inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal xor */
inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, (ir_node *)irn, get_irn_n(irn, i), nomem);
pnc = pn_ia32_Eor_res;
inverse->nodes[0] = new_rd_ia32_Eor(dbg, irg, block, noreg, noreg, (ir_node *)irn, get_irn_n(irn, i), nomem, irn_mode);
inverse->costs += 1;
}
break;
......@@ -698,8 +697,7 @@ static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, in
ir_node *proj = ia32_get_res_proj(irn);
assert(proj);
inverse->nodes[0] = new_rd_ia32_Not(NULL, irg, block, noreg, noreg, proj, nomem);
pnc = pn_ia32_Not_res;
inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, noreg, noreg, proj, nomem, irn_mode);
inverse->costs += 1;
break;
}
......@@ -707,8 +705,7 @@ static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, in
ir_node *proj = ia32_get_res_proj(irn);
assert(proj);
inverse->nodes[0] = new_rd_ia32_Minus(NULL, irg, block, noreg, noreg, proj, nomem);
pnc = pn_ia32_Minus_res;
inverse->nodes[0] = new_rd_ia32_Minus(dbg, irg, block, noreg, noreg, proj, nomem, irn_mode);
inverse->costs += 1;
break;
}
......@@ -718,7 +715,6 @@ static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, in
}
set_ia32_res_mode(inverse->nodes[0], mode);
inverse->nodes[1] = new_r_Proj(irg, block, inverse->nodes[0], mode, pnc);
return inverse;
}
......@@ -807,14 +803,8 @@ static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node
set_ia32_got_reload(irn);
set_irn_n(irn, 0, get_irg_frame(get_irn_irg(irn)));
set_irn_n(irn, 4, spill);
/*
Input at position one is index register, which is NoReg.
We would need cg object to get a real noreg, but we cannot
access it from here.
*/
set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
set_irn_n(irn, 4, spill);
//FIXME DBG_OPT_AM_S(reload, irn);
}
......@@ -867,9 +857,8 @@ ia32_irn_ops_t ia32_irn_ops = {
static void ia32_kill_convs(ia32_code_gen_t *cg) {
ir_node *irn;
/* BEWARE: the Projs are inserted in the set */
foreach_nodeset(cg->kill_conv, irn) {
ir_node *in = get_irn_n(get_Proj_pred(irn), 2);
ir_node *in = get_irn_n(irn, 2);
edges_reroute(irn, in, cg->birg->irg);
}
}
......@@ -1029,7 +1018,8 @@ static void ia32_before_ra(void *self) {
static void transform_to_Load(ia32_transform_env_t *env) {
ir_node *irn = env->irn;
ir_entity *ent = be_get_frame_entity(irn);
ir_mode *mode = get_spill_mode(env->cg, irn);
ir_mode *mode = get_irn_mode(irn);
ir_mode *spillmode = get_spill_mode(env->cg, irn);
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
ir_node *sched_point = NULL;
ir_node *ptr = get_irg_frame(env->irg);
......@@ -1041,7 +1031,7 @@ static void transform_to_Load(ia32_transform_env_t *env) {
sched_point = sched_prev(irn);
}
if (mode_is_float(mode)) {
if (mode_is_float(spillmode)) {
if (USE_SSE2(env->cg))
new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
else
......@@ -1053,7 +1043,7 @@ static void transform_to_Load(ia32_transform_env_t *env) {
set_ia32_am_support(new_op, ia32_am_Source);
set_ia32_op_type(new_op, ia32_AddrModeS);
set_ia32_am_flavour(new_op, ia32_B);
set_ia32_ls_mode(new_op, mode);
set_ia32_ls_mode(new_op, spillmode);
set_ia32_frame_ent(new_op, ent);
set_ia32_use_frame(new_op);
......@@ -1089,7 +1079,7 @@ static void transform_to_Store(ia32_transform_env_t *env) {
ir_node *nomem = new_rd_NoMem(env->irg);
ir_node *ptr = get_irg_frame(env->irg);
ir_node *val = get_irn_n(irn, be_pos_Spill_val);
ir_node *new_op, *proj;
ir_node *store;
ir_node *sched_point = NULL;
if (sched_is_scheduled(irn)) {
......@@ -1098,36 +1088,33 @@ static void transform_to_Store(ia32_transform_env_t *env) {
if (mode_is_float(mode)) {
if (USE_SSE2(env->cg))
new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
store = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
else
new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
store = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
}
else if (get_mode_size_bits(mode) == 8) {
new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
store = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
}
else {
new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
store = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
}
set_ia32_am_support(new_op, ia32_am_Dest);
set_ia32_op_type(new_op, ia32_AddrModeD);
set_ia32_am_flavour(new_op, ia32_B);
set_ia32_ls_mode(new_op, mode);
set_ia32_frame_ent(new_op, ent);
set_ia32_use_frame(new_op);
DBG_OPT_SPILL2ST(irn, new_op);
set_ia32_am_support(store, ia32_am_Dest);
set_ia32_op_type(store, ia32_AddrModeD);
set_ia32_am_flavour(store, ia32_B);
set_ia32_ls_mode(store, mode);
set_ia32_frame_ent(store, ent);
set_ia32_use_frame(store);
proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, pn_ia32_Store_M);
DBG_OPT_SPILL2ST(irn, store);
SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env->cg, irn));
if (sched_point) {
sched_add_after(sched_point, new_op);
sched_add_after(sched_point, store);
sched_remove(irn);
}
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
exchange(irn, proj);
exchange(irn, store);
}
static ir_node *create_push(ia32_transform_env_t *env, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
......@@ -1155,7 +1142,7 @@ static ir_node *create_pop(ia32_transform_env_t *env, ir_node *schedpoint, ir_no
set_ia32_frame_ent(pop, ent);
set_ia32_use_frame(pop);
set_ia32_op_type(pop, ia32_AddrModeD);
set_ia32_am_flavour(pop, ia32_B);
set_ia32_am_flavour(pop, ia32_am_OB);
set_ia32_ls_mode(pop, mode_Is);
sched_add_before(schedpoint, pop);
......
......@@ -1558,8 +1558,8 @@ static void emit_ia32_CopyB_i(const ir_node *irn, ia32_emit_env_t *emit_env) {
static void emit_ia32_Conv_with_FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
FILE *F = emit_env->out;
const lc_arg_env_t *env = ia32_get_arg_env();
ir_mode *src_mode = get_ia32_src_mode(irn);
ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
ir_mode *src_mode = get_ia32_Conv_src_mode(irn);
ir_mode *tgt_mode = get_ia32_Conv_tgt_mode(irn);
char *from, *to, buf[64];
char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
......@@ -1602,21 +1602,20 @@ static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
const lc_arg_env_t *env = ia32_get_arg_env();
char *move_cmd = "movzx";
char *conv_cmd = NULL;
ir_mode *src_mode = get_ia32_src_mode(irn);
ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
ir_mode *src_mode = get_ia32_Conv_src_mode(irn);
ir_mode *tgt_mode = get_ia32_Conv_tgt_mode(irn);
int signed_mode;
int n, m;
int src_bits = get_mode_size_bits(src_mode);
int tgt_bits = get_mode_size_bits(tgt_mode);
char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
const arch_register_t *in_reg, *out_reg;
n = get_mode_size_bits(src_mode);
m = get_mode_size_bits(tgt_mode);
assert(mode_is_int(src_mode) && mode_is_int(tgt_mode));
assert(src_bits == 8 || src_bits == 16 || src_bits == 32);
assert(tgt_bits == 8 || tgt_bits == 16 || tgt_bits == 32);
assert(src_bits != tgt_bits);
assert(n == 8 || n == 16 || n == 32);
assert(m == 8 || m == 16 || m == 32);
assert(n != m);
signed_mode = mode_is_signed(n < m ? src_mode : tgt_mode);
signed_mode = mode_is_signed(src_bits < tgt_bits ? src_mode : tgt_mode);
if(signed_mode) {
move_cmd = "movsx";
}
......@@ -1630,9 +1629,9 @@ static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
REGS_ARE_EQUAL(out_reg, in_reg) &&
signed_mode)
{
if (n == 8 || m == 8)
if (src_bits == 8 || tgt_bits == 8)
conv_cmd = "cbw";
else if (n == 16 || m == 16)
else if (src_bits == 16 || tgt_bits == 16)
conv_cmd = "cwde";
/* argument and result are both in EAX and */
......@@ -1643,13 +1642,15 @@ static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
{
/* argument and result are in the same register */
/* and signedness is ok: -> use and with mask */
int mask = (1 << (n < m ? n : m)) - 1;
int mask = (1 << (src_bits < tgt_bits ? src_bits : tgt_bits)) - 1;
lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "and %1D, 0x%x", irn, mask);
}
else {
/* use move w/o sign extension */
ir_mode *smaller_mode = src_bits < tgt_bits ? src_mode : tgt_mode;
lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %%%s",
move_cmd, irn, ia32_get_reg_name_for_mode(emit_env, n < m ? src_mode : tgt_mode, in_reg));
move_cmd, irn,
ia32_get_reg_name_for_mode(emit_env, smaller_mode, in_reg));
}
break;
......@@ -1662,7 +1663,7 @@ static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
}
lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%d Bit mode_%F -> %d Bit mode_%F) */",
irn, n, src_mode, m, tgt_mode);
irn, src_bits, src_mode, tgt_bits, tgt_mode);
IA32_DO_EMIT(irn);
}
......
......@@ -12,6 +12,7 @@
#include "ircons.h"
#include "irgmod.h"
#include "irgwalk.h"
#include "iredges.h"
#include "pdeq.h"
#include "../bearch.h"
......@@ -35,6 +36,7 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
ia32_transform_env_t tenv;
ir_node *in1, *in2, *noreg, *nomem, *res;
const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
int i, arity;
/* Return if AM node or not a Sub or xSub */
if (!(is_ia32_Sub(irn) || is_ia32_xSub(irn)) || get_ia32_op_type(irn) != ia32_Normal)
......@@ -57,43 +59,47 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
DEBUG_ONLY(tenv.mod = cg->mod;)
/* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
/* generate the neg src2 */
res = gen_Minus_ex(&tenv, in2);
arch_set_irn_register(cg->arch_env, res, in2_reg);
/* add to schedule */
sched_add_before(irn, get_Proj_pred(res));
sched_add_before(irn, res);
/* generate the add */
if (mode_is_float(tenv.mode)) {
res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
set_ia32_am_support(res, ia32_am_Source);
}
else {
res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
set_ia32_am_support(res, ia32_am_Full);
set_ia32_commutative(res);
}
set_ia32_res_mode(res, tenv.mode);
if (!REGS_ARE_EQUAL(out_reg, in2_reg))
return;
/* generate the neg src2 */
res = gen_Minus_ex(&tenv, in2);
arch_set_irn_register(cg->arch_env, res, in2_reg);
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
/* copy register */
slots = get_ia32_slots(res);
slots[0] = in2_reg;
/* add to schedule */
sched_add_before(irn, res);
/* add to schedule */
sched_add_before(irn, res);
/* generate the add */
if (mode_is_float(tenv.mode)) {
res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, tenv.mode);
set_ia32_am_support(res, ia32_am_Source);
}
else {
res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, tenv.mode);
set_ia32_am_support(res, ia32_am_Full);
set_ia32_commutative(res);
}
set_ia32_res_mode(res, tenv.mode);
/* remove the old sub */
sched_remove(irn);
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
/* copy register */
slots = get_ia32_slots(res);
slots[0] = in2_reg;
DBG_OPT_SUB2NEGADD(irn, res);
/* exchange the add and the sub */
edges_reroute(irn, res, tenv.irg);
/* exchange the add and the sub */
exchange(irn, res);
/* add to schedule */
sched_add_before(irn, res);
/* remove the old sub */
sched_remove(irn);
arity = get_irn_arity(irn);
for(i = 0; i < arity; ++i) {
set_irn_n(irn, i, new_Bad());
}
DBG_OPT_SUB2NEGADD(irn, res);
}
/**
......@@ -199,7 +205,7 @@ static void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
break;
}
res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem);
res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem, tenv.mode);
arch_set_irn_register(cg->arch_env, res, out_reg);
set_ia32_op_type(res, ia32_Normal);
set_ia32_commutative(res);
......@@ -217,11 +223,6 @@ static void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
DBG_OPT_LEA2ADD(irn, res);
res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, pn_ia32_Add_res);
/* add result Proj to schedule */
sched_add_before(irn, res);
/* remove the old LEA */
sched_remove(irn);
......
......@@ -361,14 +361,14 @@ static int DivMod_mapper(ir_node *call, void *ctx, ia32_intrinsic_divmod_t dmtp)
set_ia32_frame_ent(store_l, ent_a);
set_ia32_use_frame(store_l);
set_ia32_ls_mode(store_l, get_irn_mode(a_l));
op_mem[0] = new_r_Proj(irg, block, store_l, mode_M, pn_ia32_l_Store_M);
op_mem[0] = store_l;
store_h = new_rd_ia32_l_Store(dbg, irg, block, frame, a_h, get_irg_no_mem(irg));
set_ia32_frame_ent(store_h, ent_a);
add_ia32_am_offs_int(store_h, mode_bytes);
set_ia32_use_frame(store_h);
set_ia32_ls_mode(store_h, get_irn_mode(a_h));
op_mem[1] = new_r_Proj(irg, block, store_h, mode_M, pn_ia32_l_Store_M);
op_mem[1] = store_h;
mem = new_r_Sync(irg, block, 2, op_mem);
......@@ -385,14 +385,14 @@ static int DivMod_mapper(ir_node *call, void *ctx, ia32_intrinsic_divmod_t dmtp)
set_ia32_frame_ent(store_l, ent_b);
set_ia32_use_frame(store_l);
set_ia32_ls_mode(store_l, get_irn_mode(b_l));
op_mem[0] = new_r_Proj(irg, block, store_l, mode_M, pn_ia32_l_Store_M);
op_mem[0] = store_l;
store_h = new_rd_ia32_l_Store(dbg, irg, block, frame, b_h, get_irg_no_mem(irg));
set_ia32_frame_ent(store_h, ent_b);
add_ia32_am_offs_int(store_h, mode_bytes);
set_ia32_use_frame(store_h);
set_ia32_ls_mode(store_h, get_irn_mode(b_h));
op_mem[1] = new_r_Proj(irg, block, store_h, mode_M, pn_ia32_l_Store_M);
op_mem[1] = store_h;
mem = new_r_Sync(irg, block, 2, op_mem);
......@@ -426,7 +426,7 @@ static int DivMod_mapper(ir_node *call, void *ctx, ia32_intrinsic_divmod_t dmtp)
set_ia32_frame_ent(fres, ent_a);
set_ia32_use_frame(fres);
set_ia32_ls_mode(fres, mode_D);
mem = new_r_Proj(irg, block, fres, mode_M, pn_ia32_l_vfist_M);
mem = fres;
/* load low part of the result */
l_res = new_rd_ia32_l_Load(dbg, irg, block, frame, mem);
......@@ -508,7 +508,7 @@ static int map_Conv(ir_node *call, void *ctx) {
set_ia32_frame_ent(a_f, ent);
set_ia32_use_frame(a_f);
set_ia32_ls_mode(a_f, mode_D);
mem = new_r_Proj(irg, block, a_f, mode_M, pn_ia32_l_vfist_M);
mem = a_f;
/* load low part of the result */
l_res = new_rd_ia32_l_Load(dbg, irg, block, frame, mem);
......@@ -553,7 +553,7 @@ static int map_Conv(ir_node *call, void *ctx) {
set_ia32_frame_ent(store_l, ent);
set_ia32_use_frame(store_l);
set_ia32_ls_mode(store_l, get_irn_mode(a_l));
op_mem[0] = new_r_Proj(irg, block, store_l, mode_M, pn_ia32_l_Store_M);
op_mem[0] = store_l;
/* store second arg (high part) */
store_h = new_rd_ia32_l_Store(dbg, irg, block, frame, a_h, get_irg_no_mem(irg));
......@@ -561,7 +561,7 @@ static int map_Conv(ir_node *call, void *ctx) {
add_ia32_am_offs_int(store_h, gp_bytes);
set_ia32_use_frame(store_h);
set_ia32_ls_mode(store_h, get_irn_mode(a_h));
op_mem[1] = new_r_Proj(irg, block, store_h, mode_M, pn_ia32_l_Store_M);
op_mem[1] = store_h;
mem = new_r_Sync(irg, block, 2, op_mem);
......
......@@ -29,6 +29,7 @@
#include "firm_common_t.h"
#include "irvrfy_t.h"
#include "irprintf.h"
#include "iredges.h"
#include "../bearch.h"
......@@ -423,24 +424,6 @@ static int ia32_dump_node(ir_node *n, FILE *F, dump_reason_t reason) {
}
fprintf(F, "\n");
fprintf(F, "src_mode = ");
if (get_ia32_src_mode(n)) {
ir_fprintf(F, "%+F", get_ia32_src_mode(n));
}
else {
fprintf(F, "n/a");
}
fprintf(F, "\n");