Commit b1d47c45 authored by Christoph Mallon's avatar Christoph Mallon
Browse files

amd64, arm, ia32, sparc, template: Small cleanup in node specifications.

parent c5940669
# the cpu architecture (ia32, ia64, mips, sparc, ppc, ...)
$arch = "TEMPLATE";
#
# Modes
#
$mode_gp = "mode_Iu"; # mode used by general purpose registers
$mode_fp = "mode_F"; # mode used by floatingpoint registers
......@@ -13,12 +11,12 @@ $mode_fp = "mode_F"; # mode used by floatingpoint registers
# %nodes = (
#
# <op-name> => {
# state => "floats|pinned|mem_pinned|exc_pinned", # optional
# state => "floats|pinned|mem_pinned|exc_pinned", # optional, default floats
# comment => "any comment for constructor", # optional
# in_reqs => [ "reg_class|register" ] | "...",
# out_reqs => [ "reg_class|register|in_rX" ] | "...",
# outs => { "out1", "out2" },# optional, creates pn_op_out1, ... consts
# ins => { "in1", "in2" }, # optional, creates n_op_in1, ... consts
# outs => { "out1", "out2" },# optional, creates pn_op_out1, ... consts
# mode => "mode_Iu", # optional, predefines the mode
# emit => "emit code with templates", # optional for virtual nodes
# attr => "additional attribute arguments for constructor", # optional
......@@ -29,16 +27,8 @@ $mode_fp = "mode_F"; # mode used by floatingpoint registers
#
# ... # (all nodes you need to describe)
#
# ); # close the %nodes initializer
# );
# state: state of the operation, OPTIONAL (default is "floats")
#
# arity: arity of the operation, MUST NOT BE OMITTED
#
# outs: if a node defines more than one output, the names of the projections
# nodes having outs having automatically the mode mode_T
#
# comment: OPTIONAL comment for the node constructor
%reg_classes = (
gp => [
{ name => "r0" },
......
......@@ -3,14 +3,10 @@
$arch = "arm";
#
# Modes
#
$mode_gp = "arm_mode_gp";
$mode_flags = "arm_mode_flags";
$mode_fp = "mode_F";
# NOTE: Last entry of each class is the largest Firm-Mode a register can hold
%reg_classes = (
gp => [
{ name => "r0", dwarf => 0 },
......@@ -52,22 +48,26 @@ $default_attr_type = "arm_attr_t";
$default_copy_attr = "arm_copy_attr";
%init_attr = (
arm_attr_t => "\tinit_arm_attributes(res, irn_flags, in_reqs, n_res);",
arm_attr_t =>
"init_arm_attributes(res, irn_flags, in_reqs, n_res);",
arm_Address_attr_t =>
"\tinit_arm_attributes(res, irn_flags, in_reqs, n_res);\n".
"init_arm_attributes(res, irn_flags, in_reqs, n_res);\n".
"\tinit_arm_Address_attributes(res, entity, offset);",
arm_CondJmp_attr_t => "\tinit_arm_attributes(res, irn_flags, in_reqs, n_res);",
arm_SwitchJmp_attr_t => "\tinit_arm_attributes(res, irn_flags, in_reqs, n_res);",
arm_fConst_attr_t => "\tinit_arm_attributes(res, irn_flags, in_reqs, n_res);",
arm_CondJmp_attr_t =>
"init_arm_attributes(res, irn_flags, in_reqs, n_res);",
arm_SwitchJmp_attr_t =>
"init_arm_attributes(res, irn_flags, in_reqs, n_res);",
arm_fConst_attr_t =>
"init_arm_attributes(res, irn_flags, in_reqs, n_res);",
arm_load_store_attr_t =>
"\tinit_arm_attributes(res, irn_flags, in_reqs, n_res);\n".
"init_arm_attributes(res, irn_flags, in_reqs, n_res);\n".
"\tinit_arm_load_store_attributes(res, ls_mode, entity, entity_sign, offset, is_frame_entity);",
arm_shifter_operand_t =>
"\tinit_arm_attributes(res, irn_flags, in_reqs, n_res);\n",
"init_arm_attributes(res, irn_flags, in_reqs, n_res);",
arm_cmp_attr_t =>
"\tinit_arm_attributes(res, irn_flags, in_reqs, n_res);\n",
"init_arm_attributes(res, irn_flags, in_reqs, n_res);",
arm_farith_attr_t =>
"\tinit_arm_attributes(res, irn_flags, in_reqs, n_res);\n".
"init_arm_attributes(res, irn_flags, in_reqs, n_res);\n".
"\tinit_arm_farith_attributes(res, op_mode);",
);
......@@ -281,10 +281,10 @@ Mul => {
mode => $mode_gp,
constructors => {
"" => { out_reqs => [ "gp" ] },
# TODO: !in_r1 for out constrains the register allocator more than
# TODO: !in_r1 for out constraints the register allocator more than
# necessary, as usually you can fix the problem by swapping the inputs. But
# for this scheme we would need a special if both inputs are the same value.
"v5" => { out_reqs => [ "!in_r1" ] },
v5 => { out_reqs => [ "!in_r1" ] },
},
},
......@@ -307,7 +307,7 @@ Mla => {
constructors => {
"" => { out_reqs => [ "gp" ] },
# See comments for Mul_v5 out register constraint
"v5" => { out_reqs => [ "!in_r1" ] },
v5 => { out_reqs => [ "!in_r1" ] },
}
},
......@@ -621,9 +621,7 @@ Stf => {
attr => "ir_mode *ls_mode, ir_entity *entity, int entity_sign, long offset, bool is_frame_entity",
},
#
# floating point constants
#
fConst => {
op_flags => [ "constlike" ],
irn_flags => [ "rematerializable" ],
......@@ -698,4 +696,4 @@ OrPl_t => {
dump_func => "NULL",
},
); # end of %nodes
);
......@@ -64,65 +64,60 @@ $mode_fpcw = "ia32_mode_fpcw";
{ name => "eflags", dwarf => 9 },
{ mode => "ia32_mode_flags", flags => "manual_ra" }
],
); # %reg_classes
);
$default_attr_type = "ia32_attr_t";
$default_copy_attr = "ia32_copy_attr";
sub ia32_custom_init_attr {
my $constr = shift;
my $node = shift;
my $name = shift;
my $res = "";
my ($constr, $node, $name) = @_;
if(defined($node->{am})) {
my $res = "";
my $am = $node->{am};
if($am eq "source,unary") {
if (defined($am)) {
if ($am eq "source,unary") {
$res .= "\tset_ia32_am_support(res, ia32_am_unary);";
} elsif($am eq "source,binary") {
} elsif ($am eq "source,binary") {
$res .= "\tset_ia32_am_support(res, ia32_am_binary);";
} elsif($am eq "none") {
} elsif ($am eq "none") {
# nothing to do
} else {
die("Invalid address mode '$am' specified on op $name");
}
if($am ne "none") {
if($node->{state} ne "exc_pinned"
and $node->{state} ne "pinned") {
if ($am ne "none" && $node->{state} ne "exc_pinned" && $node->{state} ne "pinned") {
die("AM nodes must have pinned or AM pinned state ($name)");
}
}
}
return $res;
}
$custom_init_attr_func = \&ia32_custom_init_attr;
%init_attr = (
ia32_attr_t =>
"\tinit_ia32_attributes(res, irn_flags, in_reqs, n_res);",
"init_ia32_attributes(res, irn_flags, in_reqs, n_res);",
ia32_call_attr_t =>
"\tinit_ia32_attributes(res, irn_flags, in_reqs, n_res);\n".
"init_ia32_attributes(res, irn_flags, in_reqs, n_res);\n".
"\tinit_ia32_call_attributes(res, pop, call_tp);",
ia32_condcode_attr_t =>
"\tinit_ia32_attributes(res, irn_flags, in_reqs, n_res);\n".
"init_ia32_attributes(res, irn_flags, in_reqs, n_res);\n".
"\tinit_ia32_condcode_attributes(res, condition_code);",
ia32_switch_attr_t =>
"\tinit_ia32_attributes(res, irn_flags, in_reqs, n_res);\n".
"init_ia32_attributes(res, irn_flags, in_reqs, n_res);\n".
"\tinit_ia32_switch_attributes(res, switch_table);",
ia32_copyb_attr_t =>
"\tinit_ia32_attributes(res, irn_flags, in_reqs, n_res);\n".
"init_ia32_attributes(res, irn_flags, in_reqs, n_res);\n".
"\tinit_ia32_copyb_attributes(res, size);",
ia32_immediate_attr_t =>
"\tinit_ia32_attributes(res, irn_flags, in_reqs, n_res);\n".
"init_ia32_attributes(res, irn_flags, in_reqs, n_res);\n".
"\tinit_ia32_immediate_attributes(res, imm);",
ia32_x87_attr_t =>
"\tinit_ia32_attributes(res, irn_flags, in_reqs, n_res);\n".
"init_ia32_attributes(res, irn_flags, in_reqs, n_res);\n".
"\tinit_ia32_x87_attributes(res);",
ia32_climbframe_attr_t =>
"\tinit_ia32_attributes(res, irn_flags, in_reqs, n_res);\n".
"init_ia32_attributes(res, irn_flags, in_reqs, n_res);\n".
"\tinit_ia32_climbframe_attributes(res, count);",
ia32_return_attr_t =>
"\tinit_ia32_attributes(res, irn_flags, in_reqs, n_res);\n".
"init_ia32_attributes(res, irn_flags, in_reqs, n_res);\n".
"\tinit_ia32_return_attributes(res, pop);",
);
......@@ -193,7 +188,7 @@ my $shiftop_double = {
# With an immediate shift amount we can swap between ShlD/ShrD and negate
# the shift amount, if the output gets the same register as the second
# input.
"imm" => { out_reqs => [ "in_r1 in_r2", "flags" ] },
imm => { out_reqs => [ "in_r1 in_r2", "flags" ] },
},
ins => [ "val_high", "val_low", "count" ],
outs => [ "res", "flags" ],
......@@ -1033,12 +1028,8 @@ PushEax => {
Pop => {
state => "exc_pinned",
constructors => {
"" => {
out_reqs => [ "gp", "none", "mem", "esp:I" ],
},
"ebp" => {
out_reqs => [ "ebp:I", "none", "mem", "esp:I" ],
}
"" => { out_reqs => [ "gp", "none", "mem", "esp:I" ] },
ebp => { out_reqs => [ "ebp:I", "none", "mem", "esp:I" ] }
},
in_reqs => [ "mem", "esp" ],
ins => [ "mem", "stack" ],
......@@ -1117,9 +1108,7 @@ LdTls => {
latency => 1,
},
#
# BT supports source address mode, but this is unused yet
#
Bt => {
# only CF is set, but the other flags are undefined
irn_flags => [ "modify_flags", "rematerializable" ],
......@@ -1144,9 +1133,7 @@ Bsr => {
latency => 1,
},
#
# SSE4.2 or SSE4a popcnt instruction
#
Popcnt => {
template => $unop_from_mem,
emit => "popcnt%M %AS3, %D0",
......@@ -1189,11 +1176,8 @@ Call => {
latency => 4, # random number
},
#
# a Helper node for frame-climbing, needed for __builtin_(frame|return)_address
#
# PS: try gcc __builtin_frame_address(100000) :-)
#
ClimbFrame => {
irn_flags => [ "modify_flags" ],
in_reqs => [ "gp" ],
......@@ -1205,18 +1189,12 @@ ClimbFrame => {
attr => "unsigned count",
},
#
# bswap
#
Bswap => {
template => $unop_no_flags,
emit => "bswap%M %D0",
latency => 1,
},
#
# bswap16, use xchg here
#
Bswap16 => {
irn_flags => [ "rematerializable" ],
in_reqs => [ "eax ebx ecx edx" ],
......@@ -1239,27 +1217,19 @@ CmpXChgMem => {
latency => 2,
},
#
# BreakPoint
#
Breakpoint => {
template => $memop,
latency => 0,
emit => "int3",
},
#
# Undefined Instruction on ALL x86 CPU's
#
# Undefined Instruction on ALL x86 CPUs
UD2 => {
template => $memop,
latency => 0,
emit => "ud2",
},
#
# outport
#
Outport => {
irn_flags => [ "rematerializable" ],
state => "pinned",
......@@ -1271,9 +1241,6 @@ Outport => {
mode => "mode_M",
},
#
# inport
#
Inport => {
irn_flags => [ "rematerializable" ],
state => "pinned",
......@@ -1285,9 +1252,7 @@ Inport => {
latency => 1,
},
#
# Intel style prefetching
#
Prefetch0 => {
template => $prefetchop,
latency => 0,
......@@ -1312,9 +1277,7 @@ PrefetchNTA => {
emit => "prefetchnta %AM",
},
#
# 3DNow! prefetch instructions
#
Prefetch => {
template => $prefetchop,
latency => 0,
......@@ -1504,7 +1467,6 @@ CvtSI2SD => {
latency => 2,
},
l_LLtoFloat => {
ins => [ "val_high", "val_low" ],
attr_type => "",
......@@ -1829,7 +1791,6 @@ Sahf => {
# fxch, fdup, fpop
# Note that it is NEVER allowed to do CSE on these nodes
# Moreover, note the virtual register requierements!
fxch => {
op_flags => [ "keep" ],
......@@ -1884,7 +1845,7 @@ femms => {
latency => 3,
},
# Spilling and reloading of SSE registers, hardcoded, not generated #
# Spilling and reloading of SSE registers
xxLoad => {
op_flags => [ "uses_memory", "fragile" ],
......@@ -1908,27 +1869,28 @@ xxStore => {
latency => 1,
},
); # end of %nodes
);
# Transform some attributes
foreach my $op (keys(%nodes)) {
my $node = $nodes{$op};
my $op_attr_init = $node->{op_attr_init};
if(defined($op_attr_init)) {
if (defined($op_attr_init)) {
$op_attr_init .= "\n\t";
} else {
$op_attr_init = "";
}
if(!defined($node->{latency})) {
if($op =~ m/^l_/) {
$node->{latency} = 0;
my $latency = $node->{latency};
if (!defined($latency)) {
if ($op =~ m/^l_/) {
$latency = 0;
} else {
die("Latency missing for op $op");
}
}
$op_attr_init .= "ia32_init_op(op, ".$node->{latency} . ");";
$op_attr_init .= "ia32_init_op(op, $latency);";
$node->{op_attr_init} = $op_attr_init;
}
......
# Creation: 2006/02/13
$arch = "sparc";
$mode_gp = "mode_Iu";
......@@ -63,7 +61,6 @@ $mode_fp4 = "sparc_mode_Q";
{ name => "y" },
{ mode => $mode_gp, flags => "manual_ra" }
],
# fp registers can be accessed any time
fp => [
{ name => "f0", encoding => 0, dwarf => 32 },
{ name => "f1", encoding => 1, dwarf => 33 },
......@@ -99,7 +96,7 @@ $mode_fp4 = "sparc_mode_Q";
{ name => "f31", encoding => 31, dwarf => 63 },
{ mode => $mode_fp }
]
); # %reg_classes
);
$default_attr_type = "sparc_attr_t";
$default_copy_attr = "sparc_copy_attr";
......@@ -752,7 +749,7 @@ fneg => {
emit => "fnegs %S0, %D0",
},
"fabs" => {
fabs => {
template => $float_unop,
# note that we only need the first register even for wide-values
emit => "fabs %S0, %D0",
......@@ -835,4 +832,4 @@ Stf => {
mode => "mode_M",
},
); # end of %nodes
);
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