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Zwinkau
libfirm
Commits
b24c359b
Commit
b24c359b
authored
Oct 06, 2010
by
Matthias Braun
Browse files
change backends to produce 1 big array with all registers
[r28038]
parent
6730cf92
Changes
25
Hide whitespace changes
Inline
Side-by-side
ir/be/TEMPLATE/bearch_TEMPLATE.c
View file @
b24c359b
...
...
@@ -141,8 +141,10 @@ const arch_isa_if_t TEMPLATE_isa_if;
static
TEMPLATE_isa_t
TEMPLATE_isa_template
=
{
{
&
TEMPLATE_isa_if
,
/* isa interface implementation */
&
TEMPLATE_gp_regs
[
REG_SP
],
/* stack pointer register */
&
TEMPLATE_gp_regs
[
REG_BP
],
/* base pointer register */
N_TEMPLATE_REGISTERS
,
TEMPLATE_registers
,
&
TEMPLATE_registers
[
REG_SP
],
/* stack pointer register */
&
TEMPLATE_registers
[
REG_BP
],
/* base pointer register */
&
TEMPLATE_reg_classes
[
CLASS_TEMPLATE_gp
],
/* link pointer register class */
-
1
,
/* stack direction */
2
,
/* power of two stack alignment for calls, 2^2 == 4 */
...
...
@@ -195,12 +197,12 @@ static void TEMPLATE_done(void *self)
static
unsigned
TEMPLATE_get_n_reg_class
(
void
)
{
return
N_CLASSES
;
return
N_
TEMPLATE_
CLASSES
;
}
static
const
arch_register_class_t
*
TEMPLATE_get_reg_class
(
unsigned
i
)
{
assert
(
i
<
N_CLASSES
);
assert
(
i
<
N_
TEMPLATE_
CLASSES
);
return
&
TEMPLATE_reg_classes
[
i
];
}
...
...
@@ -342,7 +344,7 @@ static void TEMPLATE_get_call_abi(const void *self, ir_type *method_type,
mode
=
get_type_mode
(
tp
);
be_abi_call_res_reg
(
abi
,
0
,
mode_is_float
(
mode
)
?
&
TEMPLATE_
fp_
regs
[
REG_F0
]
:
&
TEMPLATE_
gp_
regs
[
REG_R0
],
ABI_CONTEXT_BOTH
);
mode_is_float
(
mode
)
?
&
TEMPLATE_reg
ister
s
[
REG_F0
]
:
&
TEMPLATE_reg
ister
s
[
REG_R0
],
ABI_CONTEXT_BOTH
);
}
}
...
...
ir/be/amd64/bearch_amd64.c
View file @
b24c359b
...
...
@@ -262,8 +262,10 @@ const arch_isa_if_t amd64_isa_if;
static
amd64_isa_t
amd64_isa_template
=
{
{
&
amd64_isa_if
,
/* isa interface implementation */
&
amd64_gp_regs
[
REG_RSP
],
/* stack pointer register */
&
amd64_gp_regs
[
REG_RBP
],
/* base pointer register */
N_AMD64_REGISTERS
,
amd64_registers
,
&
amd64_registers
[
REG_RSP
],
/* stack pointer register */
&
amd64_registers
[
REG_RBP
],
/* base pointer register */
&
amd64_reg_classes
[
CLASS_amd64_gp
],
/* link pointer register class */
-
1
,
/* stack direction */
3
,
/* power of two stack alignment for calls, 2^2 == 4 */
...
...
@@ -316,12 +318,12 @@ static void amd64_done(void *self)
static
unsigned
amd64_get_n_reg_class
(
void
)
{
return
N_CLASSES
;
return
N_
AMD64_
CLASSES
;
}
static
const
arch_register_class_t
*
amd64_get_reg_class
(
unsigned
i
)
{
assert
(
i
<
N_CLASSES
);
assert
(
i
<
N_
AMD64_
CLASSES
);
return
&
amd64_reg_classes
[
i
];
}
...
...
@@ -433,12 +435,12 @@ static const be_abi_callbacks_t amd64_abi_callbacks = {
};
static
const
arch_register_t
*
gpreg_param_reg_std
[]
=
{
&
amd64_
gp_
regs
[
REG_RDI
],
&
amd64_
gp_
regs
[
REG_RSI
],
&
amd64_
gp_
regs
[
REG_RDX
],
&
amd64_
gp_
regs
[
REG_RCX
],
&
amd64_
gp_
regs
[
REG_R8
],
&
amd64_
gp_
regs
[
REG_R9
],
&
amd64_reg
ister
s
[
REG_RDI
],
&
amd64_reg
ister
s
[
REG_RSI
],
&
amd64_reg
ister
s
[
REG_RDX
],
&
amd64_reg
ister
s
[
REG_RCX
],
&
amd64_reg
ister
s
[
REG_R8
],
&
amd64_reg
ister
s
[
REG_R9
],
};
static
const
arch_register_t
*
amd64_get_RegParam_reg
(
int
n
)
...
...
@@ -498,10 +500,10 @@ static void amd64_get_call_abi(const void *self, ir_type *method_type,
/* FIXME: No floating point yet */
/* be_abi_call_res_reg(abi, 0,
mode_is_float(mode) ? &amd64_fp_regs[REG_F0] : &amd64_
gp_
regs[REG_R0], ABI_CONTEXT_BOTH) */
;
mode_is_float(mode) ? &amd64_fp_regs[REG_F0] : &amd64_reg
ister
s[REG_R0], ABI_CONTEXT_BOTH) */
;
be_abi_call_res_reg
(
abi
,
0
,
&
amd64_
gp_
regs
[
REG_RAX
],
ABI_CONTEXT_BOTH
);
&
amd64_reg
ister
s
[
REG_RAX
],
ABI_CONTEXT_BOTH
);
}
}
...
...
ir/be/arm/arm_cconv.h
View file @
b24c359b
...
...
@@ -31,51 +31,51 @@
#include
"gen_arm_regalloc_if.h"
static
const
arch_register_t
*
const
callee_saves
[]
=
{
&
arm_
gp_
regs
[
REG_R4
],
&
arm_
gp_
regs
[
REG_R5
],
&
arm_
gp_
regs
[
REG_R6
],
&
arm_
gp_
regs
[
REG_R7
],
&
arm_
gp_
regs
[
REG_R8
],
&
arm_
gp_
regs
[
REG_R9
],
&
arm_
gp_
regs
[
REG_R10
],
&
arm_
gp_
regs
[
REG_R11
],
&
arm_
gp_
regs
[
REG_LR
],
&
arm_reg
ister
s
[
REG_R4
],
&
arm_reg
ister
s
[
REG_R5
],
&
arm_reg
ister
s
[
REG_R6
],
&
arm_reg
ister
s
[
REG_R7
],
&
arm_reg
ister
s
[
REG_R8
],
&
arm_reg
ister
s
[
REG_R9
],
&
arm_reg
ister
s
[
REG_R10
],
&
arm_reg
ister
s
[
REG_R11
],
&
arm_reg
ister
s
[
REG_LR
],
};
static
const
arch_register_t
*
const
caller_saves
[]
=
{
&
arm_
gp_
regs
[
REG_R0
],
&
arm_
gp_
regs
[
REG_R1
],
&
arm_
gp_
regs
[
REG_R2
],
&
arm_
gp_
regs
[
REG_R3
],
&
arm_
gp_
regs
[
REG_LR
],
&
arm_reg
ister
s
[
REG_R0
],
&
arm_reg
ister
s
[
REG_R1
],
&
arm_reg
ister
s
[
REG_R2
],
&
arm_reg
ister
s
[
REG_R3
],
&
arm_reg
ister
s
[
REG_LR
],
&
arm_
fpa_reg
s
[
REG_F0
],
&
arm_
fpa_reg
s
[
REG_F1
],
&
arm_
fpa_reg
s
[
REG_F2
],
&
arm_
fpa_reg
s
[
REG_F3
],
&
arm_
fpa_reg
s
[
REG_F4
],
&
arm_
fpa_reg
s
[
REG_F5
],
&
arm_
fpa_reg
s
[
REG_F6
],
&
arm_
fpa_reg
s
[
REG_F7
],
&
arm_
register
s
[
REG_F0
],
&
arm_
register
s
[
REG_F1
],
&
arm_
register
s
[
REG_F2
],
&
arm_
register
s
[
REG_F3
],
&
arm_
register
s
[
REG_F4
],
&
arm_
register
s
[
REG_F5
],
&
arm_
register
s
[
REG_F6
],
&
arm_
register
s
[
REG_F7
],
};
static
const
arch_register_t
*
const
param_regs
[]
=
{
&
arm_
gp_
regs
[
REG_R0
],
&
arm_
gp_
regs
[
REG_R1
],
&
arm_
gp_
regs
[
REG_R2
],
&
arm_
gp_
regs
[
REG_R3
]
&
arm_reg
ister
s
[
REG_R0
],
&
arm_reg
ister
s
[
REG_R1
],
&
arm_reg
ister
s
[
REG_R2
],
&
arm_reg
ister
s
[
REG_R3
]
};
static
const
arch_register_t
*
const
result_regs
[]
=
{
&
arm_
gp_
regs
[
REG_R0
],
&
arm_
gp_
regs
[
REG_R1
],
&
arm_
gp_
regs
[
REG_R2
],
&
arm_
gp_
regs
[
REG_R3
]
&
arm_reg
ister
s
[
REG_R0
],
&
arm_reg
ister
s
[
REG_R1
],
&
arm_reg
ister
s
[
REG_R2
],
&
arm_reg
ister
s
[
REG_R3
]
};
static
const
arch_register_t
*
const
float_result_regs
[]
=
{
&
arm_
fpa_reg
s
[
REG_F0
],
&
arm_
fpa_reg
s
[
REG_F1
]
&
arm_
register
s
[
REG_F0
],
&
arm_
register
s
[
REG_F1
]
};
/** information about a single parameter or result */
...
...
ir/be/arm/arm_emitter.c
View file @
b24c359b
...
...
@@ -519,7 +519,7 @@ static void emit_arm_CopyB(const ir_node *irn)
tmpregs
[
0
]
=
get_in_reg
(
irn
,
2
);
tmpregs
[
1
]
=
get_in_reg
(
irn
,
3
);
tmpregs
[
2
]
=
get_in_reg
(
irn
,
4
);
tmpregs
[
3
]
=
&
arm_
gp_
regs
[
REG_R12
];
tmpregs
[
3
]
=
&
arm_reg
ister
s
[
REG_R12
];
/* Note: R12 is always the last register because the RA did not assign higher ones */
qsort
((
void
*
)
tmpregs
,
3
,
sizeof
(
tmpregs
[
0
]),
reg_cmp
);
...
...
ir/be/arm/arm_map_regs.c
View file @
b24c359b
...
...
@@ -34,10 +34,10 @@
static
const
arch_register_t
*
gpreg_param_reg_std
[]
=
{
&
arm_
gp_
regs
[
REG_R0
],
&
arm_
gp_
regs
[
REG_R1
],
&
arm_
gp_
regs
[
REG_R2
],
&
arm_
gp_
regs
[
REG_R3
],
&
arm_reg
ister
s
[
REG_R0
],
&
arm_reg
ister
s
[
REG_R1
],
&
arm_reg
ister
s
[
REG_R2
],
&
arm_reg
ister
s
[
REG_R3
],
};
const
arch_register_t
*
arm_get_RegParam_reg
(
int
n
)
...
...
ir/be/arm/arm_optimize.c
View file @
b24c359b
...
...
@@ -121,7 +121,7 @@ static void peephole_be_IncSP(ir_node *node)
block
=
get_nodes_block
(
node
);
for
(
cnt
=
1
;
cnt
<
v
.
ops
;
++
cnt
)
{
int
value
=
sign
*
arm_ror
(
v
.
values
[
cnt
],
v
.
rors
[
cnt
]);
ir_node
*
next
=
be_new_IncSP
(
&
arm_
gp_
regs
[
REG_SP
],
block
,
node
,
ir_node
*
next
=
be_new_IncSP
(
&
arm_reg
ister
s
[
REG_SP
],
block
,
node
,
value
,
1
);
sched_add_after
(
node
,
next
);
node
=
next
;
...
...
@@ -150,13 +150,13 @@ static ir_node *gen_ptr_add(ir_node *node, ir_node *frame, arm_vals *v)
ir_node
*
ptr
;
ptr
=
new_bd_arm_Add_imm
(
dbgi
,
block
,
frame
,
v
->
values
[
0
],
v
->
rors
[
0
]);
arch_set_irn_register
(
ptr
,
&
arm_
gp_
regs
[
REG_R12
]);
arch_set_irn_register
(
ptr
,
&
arm_reg
ister
s
[
REG_R12
]);
sched_add_before
(
node
,
ptr
);
for
(
cnt
=
1
;
cnt
<
v
->
ops
;
++
cnt
)
{
ir_node
*
next
=
new_bd_arm_Add_imm
(
dbgi
,
block
,
ptr
,
v
->
values
[
cnt
],
v
->
rors
[
cnt
]);
arch_set_irn_register
(
next
,
&
arm_
gp_
regs
[
REG_R12
]);
arch_set_irn_register
(
next
,
&
arm_reg
ister
s
[
REG_R12
]);
sched_add_before
(
node
,
next
);
ptr
=
next
;
}
...
...
@@ -174,13 +174,13 @@ static ir_node *gen_ptr_sub(ir_node *node, ir_node *frame, arm_vals *v)
ir_node
*
ptr
;
ptr
=
new_bd_arm_Sub_imm
(
dbgi
,
block
,
frame
,
v
->
values
[
0
],
v
->
rors
[
0
]);
arch_set_irn_register
(
ptr
,
&
arm_
gp_
regs
[
REG_R12
]);
arch_set_irn_register
(
ptr
,
&
arm_reg
ister
s
[
REG_R12
]);
sched_add_before
(
node
,
ptr
);
for
(
cnt
=
1
;
cnt
<
v
->
ops
;
++
cnt
)
{
ir_node
*
next
=
new_bd_arm_Sub_imm
(
dbgi
,
block
,
ptr
,
v
->
values
[
cnt
],
v
->
rors
[
cnt
]);
arch_set_irn_register
(
next
,
&
arm_
gp_
regs
[
REG_R12
]);
arch_set_irn_register
(
next
,
&
arm_reg
ister
s
[
REG_R12
]);
sched_add_before
(
node
,
next
);
ptr
=
next
;
}
...
...
ir/be/arm/arm_transform.c
View file @
b24c359b
...
...
@@ -58,7 +58,7 @@
DEBUG_ONLY
(
static
firm_dbg_module_t
*
dbg
=
NULL
;)
static
const
arch_register_t
*
sp_reg
=
&
arm_
gp_
regs
[
REG_SP
];
static
const
arch_register_t
*
sp_reg
=
&
arm_reg
ister
s
[
REG_SP
];
static
ir_mode
*
mode_gp
;
static
ir_mode
*
mode_fp
;
static
beabi_helper_env_t
*
abihelper
;
...
...
ir/be/arm/bearch_arm.c
View file @
b24c359b
...
...
@@ -419,8 +419,10 @@ const arch_isa_if_t arm_isa_if;
static
arm_isa_t
arm_isa_template
=
{
{
&
arm_isa_if
,
/* isa interface */
&
arm_gp_regs
[
REG_SP
],
/* stack pointer */
&
arm_gp_regs
[
REG_R11
],
/* base pointer */
N_ARM_REGISTERS
,
arm_registers
,
&
arm_registers
[
REG_SP
],
/* stack pointer */
&
arm_registers
[
REG_R11
],
/* base pointer */
&
arm_reg_classes
[
CLASS_arm_gp
],
/* static link pointer class */
-
1
,
/* stack direction */
2
,
/* power of two stack alignment for calls, 2^2 == 4 */
...
...
@@ -488,7 +490,7 @@ static void arm_done(void *self)
*/
static
unsigned
arm_get_n_reg_class
(
void
)
{
return
N_CLASSES
;
return
N_
ARM_
CLASSES
;
}
/**
...
...
@@ -496,7 +498,7 @@ static unsigned arm_get_n_reg_class(void)
*/
static
const
arch_register_class_t
*
arm_get_reg_class
(
unsigned
i
)
{
assert
(
i
<
N_CLASSES
);
assert
(
i
<
N_
ARM_
CLASSES
);
return
&
arm_reg_classes
[
i
];
}
...
...
ir/be/bearch.h
View file @
b24c359b
...
...
@@ -241,8 +241,9 @@ void be_register_isa_if(const char *name, const arch_isa_if_t *isa);
struct
arch_register_t
{
const
char
*
name
;
/**< The name of the register. */
const
arch_register_class_t
*
reg_class
;
/**< The class of the register */
unsigned
index
;
/**< The index of the register in
unsigned
short
index
;
/**< The index of the register in
the class. */
unsigned
short
global_index
;
arch_register_type_t
type
;
/**< The type of the register. */
/** register constraint allowing just this register */
const
arch_register_req_t
*
single_req
;
...
...
@@ -623,6 +624,8 @@ struct arch_isa_if_t {
*/
struct
arch_env_t
{
const
arch_isa_if_t
*
impl
;
unsigned
n_registers
;
/**< number of registers */
const
arch_register_t
*
registers
;
/**< register array */
const
arch_register_t
*
sp
;
/**< The stack pointer register. */
const
arch_register_t
*
bp
;
/**< The base pointer register. */
const
arch_register_class_t
*
link_class
;
/**< The static link pointer
...
...
@@ -634,8 +637,8 @@ struct arch_env_t {
int
spill_cost
;
/**< cost for a be_Spill node */
int
reload_cost
;
/**< cost for a be_Reload node */
bool
custom_abi
:
1
;
/**< backend does all abi handling
and does not need the generic
stuff
from beabi.h/.c */
and does not need the generic
stuff
from beabi.h/.c */
};
static
inline
unsigned
arch_irn_get_n_outs
(
const
ir_node
*
node
)
...
...
ir/be/ia32/bearch_ia32.c
View file @
b24c359b
...
...
@@ -147,28 +147,28 @@ ir_node *ia32_new_NoReg_gp(ir_graph *irg)
{
ia32_irg_data_t
*
irg_data
=
ia32_get_irg_data
(
irg
);
return
create_const
(
irg
,
&
irg_data
->
noreg_gp
,
new_bd_ia32_NoReg_GP
,
&
ia32_
gp_
regs
[
REG_GP_NOREG
]);
&
ia32_reg
ister
s
[
REG_GP_NOREG
]);
}
ir_node
*
ia32_new_NoReg_vfp
(
ir_graph
*
irg
)
{
ia32_irg_data_t
*
irg_data
=
ia32_get_irg_data
(
irg
);
return
create_const
(
irg
,
&
irg_data
->
noreg_vfp
,
new_bd_ia32_NoReg_VFP
,
&
ia32_
vfp_reg
s
[
REG_VFP_NOREG
]);
&
ia32_
register
s
[
REG_VFP_NOREG
]);
}
ir_node
*
ia32_new_NoReg_xmm
(
ir_graph
*
irg
)
{
ia32_irg_data_t
*
irg_data
=
ia32_get_irg_data
(
irg
);
return
create_const
(
irg
,
&
irg_data
->
noreg_xmm
,
new_bd_ia32_NoReg_XMM
,
&
ia32_
xmm_reg
s
[
REG_XMM_NOREG
]);
&
ia32_
register
s
[
REG_XMM_NOREG
]);
}
ir_node
*
ia32_new_Fpu_truncate
(
ir_graph
*
irg
)
{
ia32_irg_data_t
*
irg_data
=
ia32_get_irg_data
(
irg
);
return
create_const
(
irg
,
&
irg_data
->
fpu_trunc_mode
,
new_bd_ia32_ChangeCW
,
&
ia32_
fp_cw_reg
s
[
REG_FPCW
]);
&
ia32_
register
s
[
REG_FPCW
]);
}
...
...
@@ -1119,7 +1119,7 @@ static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
{
dbg_info
*
dbg
=
get_irn_dbg_info
(
node
);
ir_mode
*
spmode
=
mode_Iu
;
const
arch_register_t
*
spreg
=
&
ia32_
gp_
regs
[
REG_ESP
];
const
arch_register_t
*
spreg
=
&
ia32_reg
ister
s
[
REG_ESP
];
ir_node
*
sp
;
sp
=
new_rd_Proj
(
dbg
,
pred
,
spmode
,
pos
);
...
...
@@ -1137,7 +1137,7 @@ static void transform_MemPerm(ir_node *node)
{
ir_node
*
block
=
get_nodes_block
(
node
);
ir_graph
*
irg
=
get_irn_irg
(
node
);
ir_node
*
sp
=
be_abi_get_ignore_irn
(
be_get_irg_abi
(
irg
),
&
ia32_
gp_
regs
[
REG_ESP
]);
ir_node
*
sp
=
be_abi_get_ignore_irn
(
be_get_irg_abi
(
irg
),
&
ia32_reg
ister
s
[
REG_ESP
]);
int
arity
=
be_get_MemPerm_entity_arity
(
node
);
ir_node
**
pops
=
ALLOCAN
(
ir_node
*
,
arity
);
ir_node
*
in
[
1
];
...
...
@@ -1444,8 +1444,10 @@ const arch_isa_if_t ia32_isa_if;
static
ia32_isa_t
ia32_isa_template
=
{
{
&
ia32_isa_if
,
/* isa interface implementation */
&
ia32_gp_regs
[
REG_ESP
],
/* stack pointer register */
&
ia32_gp_regs
[
REG_EBP
],
/* base pointer register */
N_IA32_REGISTERS
,
ia32_registers
,
&
ia32_registers
[
REG_ESP
],
/* stack pointer register */
&
ia32_registers
[
REG_EBP
],
/* base pointer register */
&
ia32_reg_classes
[
CLASS_ia32_gp
],
/* static link pointer register class */
-
1
,
/* stack direction */
2
,
/* power of two stack alignment, 2^2 == 4 */
...
...
@@ -1599,7 +1601,7 @@ static void ia32_done(void *self)
*/
static
unsigned
ia32_get_n_reg_class
(
void
)
{
return
N_CLASSES
;
return
N_
IA32_
CLASSES
;
}
/**
...
...
@@ -1607,7 +1609,7 @@ static unsigned ia32_get_n_reg_class(void)
*/
static
const
arch_register_class_t
*
ia32_get_reg_class
(
unsigned
i
)
{
assert
(
i
<
N_CLASSES
);
assert
(
i
<
N_
IA32_
CLASSES
);
return
&
ia32_reg_classes
[
i
];
}
...
...
@@ -1633,33 +1635,33 @@ static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
const
ir_mode
*
mode
)
{
static
const
arch_register_t
*
gpreg_param_reg_fastcall
[]
=
{
&
ia32_
gp_
regs
[
REG_ECX
],
&
ia32_
gp_
regs
[
REG_EDX
],
&
ia32_reg
ister
s
[
REG_ECX
],
&
ia32_reg
ister
s
[
REG_EDX
],
NULL
};
static
const
unsigned
MAXNUM_GPREG_ARGS
=
3
;
static
const
arch_register_t
*
gpreg_param_reg_regparam
[]
=
{
&
ia32_
gp_
regs
[
REG_EAX
],
&
ia32_
gp_
regs
[
REG_EDX
],
&
ia32_
gp_
regs
[
REG_ECX
]
&
ia32_reg
ister
s
[
REG_EAX
],
&
ia32_reg
ister
s
[
REG_EDX
],
&
ia32_reg
ister
s
[
REG_ECX
]
};
static
const
arch_register_t
*
gpreg_param_reg_this
[]
=
{
&
ia32_
gp_
regs
[
REG_ECX
],
&
ia32_reg
ister
s
[
REG_ECX
],
NULL
,
NULL
};
static
const
arch_register_t
*
fpreg_sse_param_reg_std
[]
=
{
&
ia32_
xmm_reg
s
[
REG_XMM0
],
&
ia32_
xmm_reg
s
[
REG_XMM1
],
&
ia32_
xmm_reg
s
[
REG_XMM2
],
&
ia32_
xmm_reg
s
[
REG_XMM3
],
&
ia32_
xmm_reg
s
[
REG_XMM4
],
&
ia32_
xmm_reg
s
[
REG_XMM5
],
&
ia32_
xmm_reg
s
[
REG_XMM6
],
&
ia32_
xmm_reg
s
[
REG_XMM7
]
&
ia32_
register
s
[
REG_XMM0
],
&
ia32_
register
s
[
REG_XMM1
],
&
ia32_
register
s
[
REG_XMM2
],
&
ia32_
register
s
[
REG_XMM3
],
&
ia32_
register
s
[
REG_XMM4
],
&
ia32_
register
s
[
REG_XMM5
],
&
ia32_
register
s
[
REG_XMM6
],
&
ia32_
register
s
[
REG_XMM7
]
};
static
const
arch_register_t
*
fpreg_sse_param_reg_this
[]
=
{
...
...
@@ -1805,8 +1807,8 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type,
assert
(
!
mode_is_float
(
mode
)
&&
"mixed INT, FP results not supported"
);
be_abi_call_res_reg
(
abi
,
0
,
&
ia32_
gp_
regs
[
REG_EAX
],
ABI_CONTEXT_BOTH
);
be_abi_call_res_reg
(
abi
,
1
,
&
ia32_
gp_
regs
[
REG_EDX
],
ABI_CONTEXT_BOTH
);
be_abi_call_res_reg
(
abi
,
0
,
&
ia32_reg
ister
s
[
REG_EAX
],
ABI_CONTEXT_BOTH
);
be_abi_call_res_reg
(
abi
,
1
,
&
ia32_reg
ister
s
[
REG_EDX
],
ABI_CONTEXT_BOTH
);
}
else
if
(
n
==
1
)
{
const
arch_register_t
*
reg
;
...
...
@@ -1815,7 +1817,7 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type,
assert
(
is_atomic_type
(
tp
));
mode
=
get_type_mode
(
tp
);
reg
=
mode_is_float
(
mode
)
?
&
ia32_
vfp_reg
s
[
REG_VF0
]
:
&
ia32_
gp_
regs
[
REG_EAX
];
reg
=
mode_is_float
(
mode
)
?
&
ia32_
register
s
[
REG_VF0
]
:
&
ia32_reg
ister
s
[
REG_EAX
];
be_abi_call_res_reg
(
abi
,
0
,
reg
,
ABI_CONTEXT_BOTH
);
}
...
...
ir/be/ia32/ia32_common_transform.c
View file @
b24c359b
...
...
@@ -131,7 +131,7 @@ ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val)
ir_node
*
start_block
=
get_irg_start_block
(
irg
);
ir_node
*
immediate
=
new_bd_ia32_Immediate
(
NULL
,
start_block
,
symconst
,
symconst_sign
,
no_pic_adjust
,
val
);
arch_set_irn_register
(
immediate
,
&
ia32_
gp_
regs
[
REG_GP_NOREG
]);
arch_set_irn_register
(
immediate
,
&
ia32_reg
ister
s
[
REG_GP_NOREG
]);
return
immediate
;
}
...
...
@@ -145,7 +145,7 @@ const arch_register_t *ia32_get_clobber_register(const char *clobber)
/* TODO: construct a hashmap instead of doing linear search for clobber
* register */
for
(
c
=
0
;
c
<
N_CLASSES
;
++
c
)
{
for
(
c
=
0
;
c
<
N_
IA32_
CLASSES
;
++
c
)
{
cls
=
&
ia32_reg_classes
[
c
];
for
(
r
=
0
;
r
<
cls
->
n_regs
;
++
r
)
{
const
arch_register_t
*
temp_reg
=
arch_register_for_index
(
cls
,
r
);
...
...
@@ -218,32 +218,32 @@ static void parse_asm_constraints(constraint_t *constraint, const char *c,
case
'a'
:
assert
(
cls
==
NULL
||
cls
==
&
ia32_reg_classes
[
CLASS_ia32_gp
]);
cls
=
&
ia32_reg_classes
[
CLASS_ia32_gp
];
limited
|=
1
<<
REG_EAX
;
limited
|=
1
<<
REG_
GP_
EAX
;
break
;
case
'b'
:
assert
(
cls
==
NULL
||
cls
==
&
ia32_reg_classes
[
CLASS_ia32_gp
]);
cls
=
&
ia32_reg_classes
[
CLASS_ia32_gp
];
limited
|=
1
<<
REG_EBX
;
limited
|=
1
<<
REG_
GP_
EBX
;
break
;
case
'c'
:
assert
(
cls
==
NULL
||
cls
==
&
ia32_reg_classes
[
CLASS_ia32_gp
]);
cls
=
&
ia32_reg_classes
[
CLASS_ia32_gp
];
limited
|=
1
<<
REG_ECX
;
limited
|=
1
<<
REG_
GP_
ECX
;
break
;
case
'd'
:
assert
(
cls
==
NULL
||
cls
==
&
ia32_reg_classes
[
CLASS_ia32_gp
]);
cls
=
&
ia32_reg_classes
[
CLASS_ia32_gp
];
limited
|=
1
<<
REG_EDX
;
limited
|=
1
<<
REG_
GP_
EDX
;
break
;
case
'D'
:
assert
(
cls
==
NULL
||
cls
==
&
ia32_reg_classes
[
CLASS_ia32_gp
]);
cls
=
&
ia32_reg_classes
[
CLASS_ia32_gp
];
limited
|=
1
<<
REG_EDI
;
limited
|=
1
<<
REG_
GP_
EDI
;
break
;
case
'S'
:
assert
(
cls
==
NULL
||
cls
==
&
ia32_reg_classes
[
CLASS_ia32_gp
]);
cls
=
&
ia32_reg_classes
[
CLASS_ia32_gp
];
limited
|=
1
<<
REG_ESI
;
limited
|=
1
<<
REG_
GP_
ESI
;
break
;
case
'Q'
:
case
'q'
:
...
...
@@ -251,20 +251,20 @@ static void parse_asm_constraints(constraint_t *constraint, const char *c,
* difference to Q for us (we only assign whole registers) */
assert
(
cls
==
NULL
||
cls
==
&
ia32_reg_classes
[
CLASS_ia32_gp
]);
cls
=
&
ia32_reg_classes
[
CLASS_ia32_gp
];
limited
|=
1
<<
REG_EAX
|
1
<<
REG_EBX
|
1
<<
REG_ECX
|
1
<<
REG_EDX
;
limited
|=
1
<<
REG_
GP_
EAX
|
1
<<
REG_
GP_
EBX
|
1
<<
REG_
GP_
ECX
|
1
<<
REG_
GP_
EDX
;
break
;
case
'A'
:
assert
(
cls
==
NULL
||
cls
==
&
ia32_reg_classes
[
CLASS_ia32_gp
]);
cls
=
&
ia32_reg_classes
[
CLASS_ia32_gp
];
limited
|=
1
<<
REG_EAX
|
1
<<
REG_EDX
;
limited
|=
1
<<
REG_
GP_
EAX
|
1
<<
REG_
GP_
EDX
;
break
;
case
'l'
:
assert
(
cls
==
NULL
||
cls
==
&
ia32_reg_classes
[
CLASS_ia32_gp
]);
cls
=
&
ia32_reg_classes
[
CLASS_ia32_gp
];
limited
|=
1
<<
REG_EAX
|
1
<<
REG_EBX
|
1
<<
REG_ECX
|
1
<<
REG_EDX
|
1
<<
REG_ESI
|
1
<<
REG_EDI
|
1
<<
REG_EBP
;
limited
|=
1
<<
REG_
GP_
EAX
|
1
<<
REG_
GP_
EBX
|
1
<<
REG_
GP_
ECX
|
1
<<
REG_
GP_
EDX
|
1
<<
REG_
GP_
ESI
|
1
<<
REG_
GP_
EDI
|
1
<<
REG_
GP_
EBP
;
break
;
case
'R'
:
...
...
@@ -447,7 +447,7 @@ ir_node *gen_ASM(ir_node *node)
const
ir_asm_constraint
*
out_constraints
;
ident
**
clobbers
;
int
clobbers_flags
=
0
;
unsigned
clobber_bits
[
N_CLASSES
];
unsigned
clobber_bits
[
N_
IA32_
CLASSES
];
int
out_size
;
backend_info_t
*
info
;
...
...
ir/be/ia32/ia32_emitter.c
View file @
b24c359b
...
...
@@ -154,7 +154,7 @@ static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
assert
(
reg
&&
"no in register found"
);
if
(
reg
==
&
ia32_
gp_
regs
[
REG_GP_NOREG
])
if
(
reg
==
&
ia32_reg
ister
s
[
REG_GP_NOREG
])
panic
(
"trying to emit noreg for %+F input %d"
,
irn
,
pos
);
return
reg
;
...
...
@@ -2227,14 +2227,14 @@ static unsigned char pnc_map_unsigned[8];
static
void
build_reg_map
(
void
)
{
reg_gp_map
[
REG_EAX
]
=
0x0
;
reg_gp_map
[
REG_ECX
]
=
0x1
;
reg_gp_map
[
REG_EDX
]
=
0x2
;
reg_gp_map
[
REG_EBX
]
=
0x3
;
reg_gp_map
[
REG_ESP
]
=
0x4
;
reg_gp_map
[
REG_EBP
]
=
0x5
;
reg_gp_map
[
REG_ESI
]
=
0x6
;
reg_gp_map
[
REG_EDI
]
=
0x7
;
reg_gp_map
[
REG_
GP_
EAX
]
=
0x0
;
reg_gp_map
[
REG_
GP_
ECX
]
=
0x1
;
reg_gp_map
[
REG_
GP_
EDX
]
=
0x2
;
reg_gp_map
[
REG_
GP_
EBX
]
=
0x3
;
reg_gp_map
[
REG_
GP_
ESP
]
=
0x4
;
reg_gp_map
[
REG_
GP_
EBP
]
=
0x5
;
reg_gp_map
[
REG_
GP_
ESI
]
=
0x6
;
reg_gp_map
[
REG_
GP_
EDI
]
=
0x7
;
pnc_map_signed
[
pn_Cmp_Eq
]
=
0x04
;
pnc_map_signed
[
pn_Cmp_Lt
]
=
0x0C
;
...
...
@@ -2558,7 +2558,7 @@ static void bemit_binop_with_imm(
bemit_mod_am
(
ruval
,
node
);
}
else
{
const
arch_register_t
*
reg
=
get_in_reg
(
node
,
n_ia32_binary_left
);
if
(
reg
->
index
==
REG_EAX
)
{
if
(
reg
->
index
==
REG_
GP_
EAX
)
{
bemit8
(
opcode_ax
);
}
else
{
bemit8
(
opcode
);
...
...
@@ -2663,9 +2663,9 @@ static void bemit_perm(const ir_node *node)
assert
(
cls0
==
arch_register_get_class
(
in1
)
&&
"Register class mismatch at Perm"
);
if
(
cls0
==
&
ia32_reg_classes
[
CLASS_ia32_gp
])
{
if
(
in0
->
index
==
REG_EAX
)
{
if
(
in0
->
index
==
REG_
GP_
EAX
)
{
bemit8
(
0x90
+
reg_gp_map
[
in1
->
index
]);
}
else
if
(
in1
->
index
==
REG_EAX
)
{
}
else
if
(
in1
->
index
==
REG_
GP_
EAX
)
{