Commit b5bba164 authored by Christoph Mallon's avatar Christoph Mallon
Browse files

amd64: Replace AMD64_OP_RAX_ADDR by AMD64_OP_ADDR.

parent 68d71bd2
......@@ -383,9 +383,6 @@ static void amd64_emit_am(const ir_node *const node, bool indirect_star)
return;
}
case AMD64_OP_RAX_ADDR:
amd64_emit_addr(node, &attr->addr);
return;
case AMD64_OP_IMM32:
case AMD64_OP_IMM64:
case AMD64_OP_NONE:
......
......@@ -38,7 +38,6 @@ static const char *get_op_mode_string(amd64_op_mode_t mode)
case AMD64_OP_IMM32: return "imm32";
case AMD64_OP_IMM64: return "imm64";
case AMD64_OP_NONE: return "none";
case AMD64_OP_RAX_ADDR: return "rax_addr";
case AMD64_OP_RAX_REG: return "rax_reg";
case AMD64_OP_REG_ADDR: return "reg+addr";
case AMD64_OP_REG_IMM: return "reg+imm";
......
......@@ -44,7 +44,6 @@ static inline bool amd64_has_addr_attr(const ir_node *node)
|| attr->op_mode == AMD64_OP_UNOP_ADDR
|| attr->op_mode == AMD64_OP_UNOP_IMM32
|| attr->op_mode == AMD64_OP_UNOP_REG
|| attr->op_mode == AMD64_OP_RAX_ADDR
|| attr->op_mode == AMD64_OP_RAX_REG)
&& !is_amd64_xor_0(node)
&& !is_amd64_xorpd_0(node);
......
......@@ -59,7 +59,6 @@ typedef enum {
/** A binary operation with 1 operand being RAX (which is usually not
* explicitly given in the assembly) */
AMD64_OP_RAX_REG,
AMD64_OP_RAX_ADDR,
} amd64_op_mode_t;
enum {
......
......@@ -776,7 +776,7 @@ static ir_node *gen_binop_rax(ir_node *node, ir_node *op1, ir_node *op2,
addr.mem_input = mem_input;
mem_proj = get_Proj_for_pn(load, pn_Load_M);
op_mode = AMD64_OP_RAX_ADDR;
op_mode = AMD64_OP_ADDR;
} else {
/* simply transform the arguments */
in[arity++] = be_transform_node(op1);
......
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