Commit b731214f authored by Matthias Braun's avatar Matthias Braun
Browse files

introduce be_lv_foreach_cls and use it

parent 5dd864dc
......@@ -315,16 +315,14 @@ static void assign(ir_node *const block, void *const env_ptr)
/* Add initial defs for all values live in.
* Since their colors have already been assigned (The dominators were
* allocated before), we have to mark their colors as used also. */
be_lv_foreach(lv, block, be_lv_state_in, irn) {
if (arch_irn_consider_in_reg_alloc(env->cls, irn)) {
arch_register_t const *const reg = arch_get_irn_register(irn);
be_lv_foreach_cls(lv, block, be_lv_state_in, env->cls, irn) {
arch_register_t const *const reg = arch_get_irn_register(irn);
assert(reg && "Node must have been assigned a register");
DBG((dbg, LEVEL_4, "%+F has reg %s\n", irn, reg->name));
assert(reg && "Node must have been assigned a register");
DBG((dbg, LEVEL_4, "%+F has reg %s\n", irn, reg->name));
/* Mark the color of the live in value as used. */
bitset_clear(available, reg->index);
}
/* Mark the color of the live in value as used. */
bitset_clear(available, reg->index);
}
/* Mind that the sequence of defs from back to front defines a perfect
......
......@@ -128,12 +128,10 @@ void create_borders(ir_node *block, void *env_ptr)
* Make final uses of all values live out of the block.
* They are necessary to build up real intervals.
*/
be_lv_foreach(lv, block, be_lv_state_end, irn) {
if (arch_irn_consider_in_reg_alloc(env->cls, irn)) {
DBG((dbg, LEVEL_3, "\tMaking live: %+F/%d\n", irn, get_irn_idx(irn)));
bitset_set(live, get_irn_idx(irn));
border_use(irn, step, 0);
}
be_lv_foreach_cls(lv, block, be_lv_state_end, env->cls, irn) {
DB((dbg, LEVEL_3, "\tMaking live: %+F/%d\n", irn, get_irn_idx(irn)));
bitset_set(live, get_irn_idx(irn));
border_use(irn, step, 0);
}
++step;
......
......@@ -359,21 +359,19 @@ static void draw_block(ir_node *bl, void *data)
if (dom) {
struct block_dims *dom_dims = pmap_get(struct block_dims, env->block_dims, dom);
be_lv_foreach(lv, bl, be_lv_state_in, irn) {
if (arch_irn_consider_in_reg_alloc(env->cls, irn)) {
const arch_register_t *reg = arch_get_irn_register(irn);
int x = (reg->index + 1) * opts->h_inter_gap;
color_t color;
reg_to_color(env, bl, irn, &color);
env->plotter->vtab->set_color(env->plotter, &color);
env->plotter->vtab->line(env->plotter,
dims->box.x + x,
dims->box.y + dims->box.h,
dom_dims->box.x + x,
dom_dims->box.y);
}
be_lv_foreach_cls(lv, bl, be_lv_state_in, env->cls, irn) {
const arch_register_t *reg = arch_get_irn_register(irn);
int x = (reg->index + 1) * opts->h_inter_gap;
color_t color;
reg_to_color(env, bl, irn, &color);
env->plotter->vtab->set_color(env->plotter, &color);
env->plotter->vtab->line(env->plotter,
dims->box.x + x,
dims->box.y + dims->box.h,
dom_dims->box.x + x,
dom_dims->box.y);
}
}
}
......
......@@ -506,10 +506,7 @@ void be_liveness_end_of_block(const be_lv_t *lv,
const ir_node *block, ir_nodeset_t *live)
{
assert(lv->sets_valid && "live sets must be computed");
be_lv_foreach(lv, block, be_lv_state_end, node) {
if (!arch_irn_consider_in_reg_alloc(cls, node))
continue;
be_lv_foreach_cls(lv, block, be_lv_state_end, cls, node) {
ir_nodeset_insert(live, node);
}
}
......
......@@ -31,6 +31,7 @@
#include "irhooks.h"
#include "irlivechk.h"
#include "belive.h"
#include "bearch.h"
#define be_is_live_in(lv, bl, irn) _be_is_live_xxx(lv, bl, irn, be_lv_state_in)
#define be_is_live_end(lv, bl, irn) _be_is_live_xxx(lv, bl, irn, be_lv_state_end)
......@@ -103,9 +104,32 @@ static inline ir_node *be_lv_iteration_next(lv_iterator_t *iterator, be_lv_state
return NULL;
}
static inline ir_node *be_lv_iteration_cls_next(lv_iterator_t *iterator, be_lv_state_t flags, const arch_register_class_t *cls)
{
while (iterator->i != 0) {
const be_lv_info_t *info = iterator->info + iterator->i--;
if (!(info->node.flags & flags))
continue;
ir_node *node = info->node.node;
ir_mode *mode = get_irn_mode(node);
if (!mode_is_datab(mode))
continue;
if (!arch_irn_consider_in_reg_alloc(cls, node))
continue;
return node;
}
return NULL;
}
#define be_lv_foreach(lv, block, flags, node) \
for (bool once = true; once;) \
for (lv_iterator_t iter = be_lv_iteration_begin((lv), (block)); once; once = false) \
for (ir_node *node; (node = be_lv_iteration_next(&iter, (flags))) != NULL;)
#define be_lv_foreach_cls(lv, block, flags, cls, node) \
for (bool once = true; once;) \
for (lv_iterator_t iter = be_lv_iteration_begin((lv), (block)); once; once = false) \
for (ir_node *node; (node = be_lv_iteration_cls_next(&iter, (flags), (cls))) != NULL;)
#endif
......@@ -603,9 +603,8 @@ static void decide_start_workset(const ir_node *block)
}
/* check all Live-Ins */
be_lv_foreach(lv, block, be_lv_state_in, node) {
be_lv_foreach_cls(lv, block, be_lv_state_in, cls, node) {
unsigned available;
if (all_preds_known) {
available = available_in_all_preds(pred_worksets, arity, node, false);
} else {
......
......@@ -300,10 +300,7 @@ static block_info_t *compute_block_start_state(minibelady_env_t *env, ir_node *b
}
/* check all Live-Ins */
be_lv_foreach(env->lv, block, be_lv_state_in, node) {
if (!mode_is_data(get_irn_mode(node)))
continue;
be_lv_foreach_cls(env->lv, block, be_lv_state_in, env->reg->reg_class, node) {
if (arch_get_irn_register(node) != env->reg)
continue;
......
......@@ -607,12 +607,8 @@ static fp_liveness fp_liveness_end_of_block(x87_simulator *sim, const ir_node *b
const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_fp];
const be_lv_t *lv = sim->lv;
be_lv_foreach(lv, block, be_lv_state_end, node) {
const arch_register_t *reg;
if (!arch_irn_consider_in_reg_alloc(cls, node))
continue;
reg = x87_get_irn_register(node);
be_lv_foreach_cls(lv, block, be_lv_state_end, cls, node) {
const arch_register_t *reg = x87_get_irn_register(node);
live |= 1 << reg->index;
}
......
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