Commit b7a411f5 authored by Matthias Braun's avatar Matthias Braun
Browse files

ia32: create specific modes instead of using deprecated firm predefined ones

parent 5f0018d1
......@@ -75,8 +75,12 @@ transformer_t be_transformer = TRANSFORMER_DEFAULT;
#endif
ir_mode *ia32_mode_fpcw;
ir_mode *ia32_mode_flags;
ir_mode *ia32_mode_E;
ir_type *ia32_type_E;
ir_mode *ia32_mode_gp;
ir_mode *ia32_mode_float64;
ir_mode *ia32_mode_float32;
/** The current omit-fp state */
static ir_type *omit_fp_between_type = NULL;
......@@ -213,8 +217,8 @@ static void ia32_build_between_type(void)
{
#define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
if (between_type == NULL) {
ir_type *old_bp_type = new_type_primitive(mode_Iu);
ir_type *ret_addr_type = new_type_primitive(mode_Iu);
ir_type *old_bp_type = new_type_primitive(ia32_mode_gp);
ir_type *ret_addr_type = new_type_primitive(ia32_mode_gp);
between_type = new_type_struct(IDENT("ia32_between_type"));
old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
......@@ -303,9 +307,9 @@ static int ia32_get_op_estimated_cost(ir_node const *const irn)
static ir_mode *get_spill_mode_mode(const ir_mode *mode)
{
if (mode_is_float(mode))
return precise_x87_spills ? ia32_mode_E : mode_D;
return precise_x87_spills ? ia32_mode_E : ia32_mode_float64;
return mode_Iu;
return ia32_mode_gp;
}
/**
......@@ -334,7 +338,7 @@ static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
return 0;
if (mode_is_float(mode)) {
ir_mode *spillmode = get_spill_mode_mode(mode);
if (spillmode != mode_D && spillmode != mode_F)
if (spillmode != ia32_mode_float64 && spillmode != mode_F)
return 0;
}
......@@ -440,7 +444,7 @@ ir_node *ia32_turn_back_am(ir_node *node)
ir_node *noreg;
ir_node *load = new_bd_ia32_Load(dbgi, block, base, idx, mem);
ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
ir_node *load_res = new_rd_Proj(dbgi, load, ia32_mode_gp, pn_ia32_Load_res);
ia32_copy_am_attrs(load, node);
if (is_ia32_is_reload(node))
......@@ -651,7 +655,7 @@ static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_
set_ia32_frame_ent(push, ent);
set_ia32_use_frame(push);
set_ia32_op_type(push, ia32_AddrModeS);
set_ia32_ls_mode(push, mode_Is);
set_ia32_ls_mode(push, ia32_mode_gp);
set_ia32_is_spill(push);
sched_add_before(schedpoint, push);
......@@ -672,7 +676,7 @@ static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_e
set_ia32_frame_ent(pop, ent);
set_ia32_use_frame(pop);
set_ia32_op_type(pop, ia32_AddrModeD);
set_ia32_ls_mode(pop, mode_Is);
set_ia32_ls_mode(pop, ia32_mode_gp);
set_ia32_is_reload(pop);
sched_add_before(schedpoint, pop);
......@@ -683,7 +687,7 @@ static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_e
static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
{
dbg_info *dbgi = get_irn_dbg_info(node);
ir_mode *spmode = mode_Iu;
ir_mode *spmode = ia32_mode_gp;
const arch_register_t *spreg = &ia32_registers[REG_ESP];
ir_node *sp;
......@@ -836,7 +840,7 @@ need_stackent:
const ia32_attr_t *attr = get_ia32_attr_const(node);
if (attr->data.need_32bit_stackent) {
mode = mode_Is;
mode = ia32_mode_gp;
} else if (attr->data.need_64bit_stackent) {
mode = mode_Ls;
} else {
......@@ -858,7 +862,7 @@ need_stackent:
case iro_ia32_FldCW: {
/* although 2 byte would be enough 4 byte performs best */
mode = mode_Iu;
mode = ia32_mode_gp;
align = 4;
break;
}
......@@ -966,7 +970,7 @@ static void introduce_prolog_epilog(ir_graph *irg)
unsigned frame_size = get_type_size_bytes(frame_type);
be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
ir_node *initial_sp = be_get_initial_reg_value(irg, sp);
ir_mode *mode_gp = mode_Iu;
ir_mode *mode_gp = ia32_mode_gp;
if (!layout->sp_relative) {
/* push ebp */
......@@ -1378,8 +1382,8 @@ static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node
ir_graph *const irg = get_irn_irg(block);
ir_node * p = trampoline;
ir_mode *const mode = get_irn_mode(p);
ir_node *const one = new_r_Const(irg, get_mode_one(mode_Iu));
ir_node *const four = new_r_Const_long(irg, mode_Iu, 4);
ir_node *const one = new_r_Const(irg, get_mode_one(ia32_mode_gp));
ir_node *const four = new_r_Const_long(irg, ia32_mode_gp, 4);
ir_node * st;
/* mov ecx,<env> */
......@@ -1440,7 +1444,8 @@ static void ia32_init(void)
init_asm_constraints();
ia32_mode_fpcw = new_int_mode("Fpcw", irma_twos_complement, 16, 0, 0);
ia32_mode_fpcw = new_non_arithmetic_mode("fpcw");
ia32_mode_flags = new_non_arithmetic_mode("flags");
/* note mantissa is 64bit but with explicitely encoded 1 so the really
* usable part as counted by firm is only 63 bits */
......@@ -1449,6 +1454,10 @@ static void ia32_init(void)
set_type_size_bytes(ia32_type_E, 12);
set_type_alignment_bytes(ia32_type_E, 4);
ia32_mode_gp = new_int_mode("gp", irma_twos_complement, 32, 0, 32);
ia32_mode_float64 = new_float_mode("fp64", irma_ieee754, 11, 52);
ia32_mode_float32 = new_float_mode("fp32", irma_ieee754, 8, 23);
mode_long_long = new_int_mode("long long", irma_twos_complement, 64, 1, 64);
type_long_long = new_type_primitive(mode_long_long);
mode_unsigned_long_long
......@@ -1664,7 +1673,7 @@ static void ia32_get_call_abi(ir_type *method_type, be_abi_call_t *abi)
pop_amount += (size + 3U) & ~3U;
}
if (size < 4) load_mode = mode_Iu;
if (size < 4) load_mode = ia32_mode_gp;
}
be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
......@@ -1777,7 +1786,7 @@ static void ia32_lower_for_target(void)
for (size_t i = 0; i < n_irgs; ++i) {
ir_graph *irg = get_irp_irg(i);
/* lower for mode_b stuff */
ir_lower_mode_b(irg, mode_Iu);
ir_lower_mode_b(irg, ia32_mode_gp);
be_after_transform(irg, "lower-modeb");
}
......
......@@ -75,6 +75,10 @@ extern ir_mode *ia32_mode_fpcw;
/** extended floatingpoint mode */
extern ir_mode *ia32_mode_E;
extern ir_type *ia32_type_E;
extern ir_mode *ia32_mode_gp;
extern ir_mode *ia32_mode_float64;
extern ir_mode *ia32_mode_float32;
extern ir_mode *ia32_mode_flags;
static inline ia32_irg_data_t *ia32_get_irg_data(const ir_graph *irg)
{
......
......@@ -129,11 +129,7 @@ const arch_register_t *ia32_get_clobber_register(const char *clobber)
bool ia32_mode_needs_gp_reg(ir_mode *mode)
{
if (mode == ia32_mode_fpcw)
return false;
if (get_mode_size_bits(mode) > 32)
return false;
return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
return get_mode_arithmetic(mode) == irma_twos_complement;
}
/**
......
......@@ -598,7 +598,7 @@ emit_I:
case 'M': {
ir_mode *mode = get_ia32_ls_mode(node);
if (!mode)
mode = mode_Iu;
mode = ia32_mode_gp;
if (mod & EMIT_RESPECT_LS) {
if (get_mode_size_bits(mode) == 32)
break;
......
......@@ -130,7 +130,7 @@ carry:;
if (flags_proj != NULL) {
set_irn_mode(adc, mode_T);
ir_node *adc_flags = new_r_Proj(adc, mode_Iu, pn_ia32_Adc_flags);
ir_node *adc_flags = new_r_Proj(adc, ia32_mode_gp, pn_ia32_Adc_flags);
arch_set_irn_register(adc_flags, &ia32_registers[REG_EFLAGS]);
ir_node *cmc = new_bd_ia32_Cmc(dbgi, block, adc_flags);
......
......@@ -92,8 +92,8 @@ static ir_node *create_fpu_mode_spill(void *env, ir_node *state, bool force,
ir_node *spill
= new_bd_ia32_FnstCW(NULL, block, frame, noreg, nomem, state);
set_ia32_op_type(spill, ia32_AddrModeD);
/* use mode_Iu, as movl has a shorter opcode than movw */
set_ia32_ls_mode(spill, mode_Iu);
/* use ia32_mode_gp, as movl has a shorter opcode than movw */
set_ia32_ls_mode(spill, ia32_mode_gp);
set_ia32_use_frame(spill);
sched_add_after(skip_Proj(after), spill);
......@@ -153,7 +153,7 @@ static ir_node *create_fpu_mode_reload(void *env, ir_node *state,
sched_add_before(before, reload);
} else {
ir_mode *lsmode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
ir_mode *lsmode = mode_Hu;
ir_node *nomem = get_irg_no_mem(irg);
ir_node *cwstore, *load, *load_res, *orn, *store, *fldcw;
ir_node *store_proj;
......@@ -173,7 +173,7 @@ static ir_node *create_fpu_mode_reload(void *env, ir_node *state,
set_ia32_use_frame(load);
sched_add_before(before, load);
load_res = new_r_Proj(load, mode_Iu, pn_ia32_Load_res);
load_res = new_r_Proj(load, ia32_mode_gp, pn_ia32_Load_res);
/* TODO: make the actual mode configurable in ChangeCW... */
or_const = new_bd_ia32_Immediate(NULL, get_irg_start_block(irg),
......@@ -185,8 +185,8 @@ static ir_node *create_fpu_mode_reload(void *env, ir_node *state,
store = new_bd_ia32_Store(NULL, block, frame, noreg, nomem, orn);
set_ia32_op_type(store, ia32_AddrModeD);
/* use mode_Iu, as movl has a shorter opcode than movw */
set_ia32_ls_mode(store, mode_Iu);
/* use ia32_mode_gp, as movl has a shorter opcode than movw */
set_ia32_ls_mode(store, ia32_mode_gp);
set_ia32_use_frame(store);
store_proj = new_r_Proj(store, mode_M, pn_ia32_Store_M);
sched_add_before(before, store);
......
......@@ -45,7 +45,7 @@ static void ia32_lower_add64(ir_node *node, ir_mode *mode)
ir_node *add_low
= new_bd_ia32_l_Add(dbg, block, left_low, right_low);
ir_mode *mode_flags = ia32_reg_classes[CLASS_ia32_flags].mode;
ir_node *res_low = new_r_Proj(add_low, mode_Iu, pn_ia32_l_Add_res);
ir_node *res_low = new_r_Proj(add_low, ia32_mode_gp, pn_ia32_l_Add_res);
ir_node *flags = new_r_Proj(add_low, mode_flags, pn_ia32_l_Add_flags);
/* h_res = a_h + b_h + carry */
......@@ -73,7 +73,7 @@ static void ia32_lower_sub64(ir_node *node, ir_mode *mode)
ir_node *sub_low
= new_bd_ia32_l_Sub(dbg, block, left_low, right_low);
ir_mode *mode_flags = ia32_reg_classes[CLASS_ia32_flags].mode;
ir_node *res_low = new_r_Proj(sub_low, mode_Iu, pn_ia32_l_Sub_res);
ir_node *res_low = new_r_Proj(sub_low, ia32_mode_gp, pn_ia32_l_Sub_res);
ir_node *flags = new_r_Proj(sub_low, mode_flags, pn_ia32_l_Sub_flags);
/* h_res = a_h - b_h - carry */
......@@ -145,12 +145,12 @@ static void ia32_lower_mul64(ir_node *node, ir_mode *mode)
&& is_sign_extend(right_low, right_high)) {
ir_node *mul = new_bd_ia32_l_IMul(dbg, block, left_low, right_low);
h_res = new_rd_Proj(dbg, mul, mode, pn_ia32_l_IMul_res_high);
l_res = new_rd_Proj(dbg, mul, mode_Iu, pn_ia32_l_IMul_res_low);
l_res = new_rd_Proj(dbg, mul, ia32_mode_gp, pn_ia32_l_IMul_res_low);
} else {
/* note that zero extension is handled hare efficiently */
ir_node *mul = new_bd_ia32_l_Mul(dbg, block, left_low, right_low);
ir_node *pEDX = new_rd_Proj(dbg, mul, mode, pn_ia32_l_Mul_res_high);
l_res = new_rd_Proj(dbg, mul, mode_Iu, pn_ia32_l_Mul_res_low);
l_res = new_rd_Proj(dbg, mul, ia32_mode_gp, pn_ia32_l_Mul_res_low);
ir_node *right_lowc = new_rd_Conv(dbg, block, right_low, mode);
ir_node *mul1 = new_rd_Mul(dbg, block, left_high, right_lowc, mode);
......@@ -173,7 +173,7 @@ static void ia32_lower_minus64(ir_node *node, ir_mode *mode)
ir_node *op_low = get_lowered_low(op);
ir_node *op_high = get_lowered_high(op);
ir_node *minus = new_bd_ia32_l_Minus64(dbg, block, op_low, op_high);
ir_node *l_res = new_r_Proj(minus, mode_Iu, pn_ia32_Minus64_res_low);
ir_node *l_res = new_r_Proj(minus, ia32_mode_gp, pn_ia32_Minus64_res_low);
ir_node *h_res = new_r_Proj(minus, mode, pn_ia32_Minus64_res_high);
ir_set_dw_lowered(node, l_res, h_res);
}
......@@ -198,7 +198,7 @@ static void ia32_lower_conv64(ir_node *node, ir_mode *mode)
/* convert from float to signed 64bit */
ir_node *block = get_nodes_block(node);
float_to_ll = new_bd_ia32_l_FloattoLL(dbg, block, op);
l_res = new_r_Proj(float_to_ll, mode_Iu,
l_res = new_r_Proj(float_to_ll, ia32_mode_gp,
pn_ia32_l_FloattoLL_res_low);
h_res = new_r_Proj(float_to_ll, mode,
pn_ia32_l_FloattoLL_res_high);
......@@ -248,7 +248,7 @@ static void ia32_lower_conv64(ir_node *node, ir_mode *mode)
add_Block_phi(lower_blk, flt_phi);
float_to_ll = new_bd_ia32_l_FloattoLL(dbg, lower_blk, flt_phi);
l_res = new_r_Proj(float_to_ll, mode_Iu,
l_res = new_r_Proj(float_to_ll, ia32_mode_gp,
pn_ia32_l_FloattoLL_res_low);
h_res = new_r_Proj(float_to_ll, mode,
pn_ia32_l_FloattoLL_res_high);
......
......@@ -253,7 +253,7 @@ static void peephole_ia32_Test(ir_node *node)
/* If there are other users, reroute them to result proj */
if (get_irn_n_edges(op) != 2) {
ir_node *res = new_r_Proj(op, mode_Iu, pn_ia32_res);
ir_node *res = new_r_Proj(op, ia32_mode_gp, pn_ia32_res);
edges_reroute_except(op, res, res);
}
} else {
......@@ -621,7 +621,7 @@ static void peephole_Load_IncSP_to_pop(ir_node *irn)
copy_mark(load, pop);
/* create stackpointer Proj */
pred_sp = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
pred_sp = new_r_Proj(pop, ia32_mode_gp, pn_ia32_Pop_stack);
arch_set_irn_register(pred_sp, esp);
sched_add_before(irn, pop);
......@@ -687,9 +687,9 @@ static ir_node *create_pop(dbg_info *dbgi, ir_node *block,
pop = new_bd_ia32_Pop(dbgi, block, get_irg_no_mem(irg), stack);
stack = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
stack = new_r_Proj(pop, ia32_mode_gp, pn_ia32_Pop_stack);
arch_set_irn_register(stack, esp);
val = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_res);
val = new_r_Proj(pop, ia32_mode_gp, pn_ia32_Pop_res);
arch_set_irn_register(val, reg);
sched_add_before(schedpoint, pop);
......
......@@ -14,8 +14,7 @@
#include "firm_types.h"
/**
* Prepares irg for codegeneration. Places consts and transform reference mode
* nodes into mode_Iu nodes.
* Prepares irg for codegeneration.
*/
void ia32_pre_transform_phase(ir_graph *irg);
......
......@@ -2,11 +2,11 @@
$arch = "ia32";
$mode_xmm = "mode_D";
$mode_mmx = "mode_D";
$mode_xmm = "ia32_mode_float64";
$mode_mmx = "ia32_mode_float64";
$mode_fp87 = "ia32_mode_E";
$mode_gp = "mode_Iu";
$mode_flags = "mode_Iu";
$mode_gp = "ia32_mode_gp";
$mode_flags = "ia32_mode_flags";
$mode_fpcw = "ia32_mode_fpcw";
%reg_classes = (
......@@ -63,7 +63,7 @@ $mode_fpcw = "ia32_mode_fpcw";
],
flags => [
{ name => "eflags", dwarf => 9 },
{ mode => "mode_Iu", flags => "manual_ra" }
{ mode => "ia32_mode_flags", flags => "manual_ra" }
],
); # %reg_classes
......
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