amd64: support 128bit xmm consts

ir/be/amd64/amd64_spec.pl

@@ -649,6 +649,17 @@ CvtSI2SD => {
 	emit      => "cvtsi2sd %AM, %^D0",
 },
 
+movdqa => {
+	state     => "exc_pinned",
+	arity     => "variable",
+	outs      => [ "res", "none", "M" ],
+	reg_req   => { out => [ "xmm", "none", "none" ] },
+	attr_type => "amd64_addr_attr_t",
+	attr      => "amd64_op_mode_t op_mode, amd64_addr_t addr",
+	fixed     => "amd64_insn_mode_t insn_mode = INSN_MODE_128;\n",
+	emit      => "movdqa %AM, %D0",
+},
+
 movdqu => {
 	state     => "exc_pinned",
 	arity     => "variable",

ir/be/amd64/amd64_transform.c

@@ -392,12 +392,18 @@ static ir_node *create_float_const(dbg_info *dbgi, ir_node *block,
 		addr.base_input = RIP_INPUT;
 	}
 
-	ir_node *load = new_bd_amd64_xMovs(dbgi, block, ARRAY_SIZE(in), in,
-	                                   insn_mode, AMD64_OP_ADDR, addr);
-
+	ir_node *load;
+	if (insn_mode == INSN_MODE_128) {
+		load = new_bd_amd64_movdqa(dbgi, block, ARRAY_SIZE(in), in,
+		                           AMD64_OP_ADDR, addr);
+	} else {
+		load = new_bd_amd64_xMovs(dbgi, block, ARRAY_SIZE(in), in,
+		                          insn_mode, AMD64_OP_ADDR, addr);
+	}
 	arch_set_irn_register_reqs_in(load, mem_reqs);
 	set_irn_pinned(load, op_pin_state_floats);
 
+	assert((unsigned)pn_amd64_xMovs_res == (unsigned)pn_amd64_movdqa_res);
 	return new_r_Proj(load, tv_mode, pn_amd64_xMovs_res);
 }