ia32_x87: remove the distinction between vfp and fp concepts

It's really the same stuff just before and after running ia32_x87
simulator, there is no real need to have 2 different things.

ir/be/ia32/bearch_ia32.c

@@ -148,11 +148,11 @@ ir_node *ia32_new_NoReg_gp(ir_graph *irg)
 	                    &ia32_registers[REG_GP_NOREG]);
 }
 
-ir_node *ia32_new_NoReg_vfp(ir_graph *irg)
+ir_node *ia32_new_NoReg_fp(ir_graph *irg)
 {
 	ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
-	return create_const(irg, &irg_data->noreg_vfp, new_bd_ia32_NoReg_VFP,
-	                    &ia32_registers[REG_VFP_NOREG]);
+	return create_const(irg, &irg_data->noreg_fp, new_bd_ia32_NoReg_FP,
+	                    &ia32_registers[REG_FP_NOREG]);
 }
 
 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
@@ -185,7 +185,7 @@ static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
 	if (ia32_cg_config.use_sse2) {
 		return ia32_new_NoReg_xmm(irg);
 	} else {
-		return ia32_new_NoReg_vfp(irg);
+		return ia32_new_NoReg_fp(irg);
 	}
 }
 
@@ -816,7 +816,7 @@ static void transform_to_Load(ir_node *node)
 		if (ia32_cg_config.use_sse2)
 			new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
 		else
-			new_op = new_bd_ia32_vfld(dbgi, block, ptr, noreg, mem, spillmode);
+			new_op = new_bd_ia32_fld(dbgi, block, ptr, noreg, mem, spillmode);
 	}
 	else if (get_mode_size_bits(spillmode) == 128) {
 		/* Reload 128 bit SSE registers */
@@ -877,8 +877,8 @@ static void transform_to_Store(ir_node *node)
 			store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
 			res   = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
 		} else {
-			store = new_bd_ia32_vfst(dbgi, block, ptr, noreg, nomem, val, mode);
-			res   = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
+			store = new_bd_ia32_fst(dbgi, block, ptr, noreg, nomem, val, mode);
+			res   = new_r_Proj(store, mode_M, pn_ia32_fst_M);
 		}
 	} else if (get_mode_size_bits(mode) == 128) {
 		/* Spill 128 bit SSE registers */
@@ -1111,8 +1111,8 @@ need_stackent:
 				break;
 			}
 
-			case iro_ia32_vfild:
-			case iro_ia32_vfld:
+			case iro_ia32_fild:
+			case iro_ia32_fld:
 			case iro_ia32_xLoad: {
 				mode  = get_ia32_ls_mode(node);
 				align = 4;
@@ -1134,9 +1134,8 @@ need_stackent:
 			case iro_ia32_Store8Bit:
 			case iro_ia32_Store:
 			case iro_ia32_fst:
-			case iro_ia32_vfist:
-			case iro_ia32_vfisttp:
-			case iro_ia32_vfst:
+			case iro_ia32_fist:
+			case iro_ia32_fisttp:
 			case iro_ia32_xStore:
 			case iro_ia32_xStoreSimple:
 #endif
@@ -1993,7 +1992,7 @@ static void ia32_get_call_abi(ir_type *method_type, be_abi_call_t *abi)
 		const arch_register_t *reg;
 		assert(is_atomic_type(tp));
 
-		reg = mode_is_float(mode) ? &ia32_registers[REG_VF0] : &ia32_registers[REG_EAX];
+		reg = mode_is_float(mode) ? &ia32_registers[REG_ST0] : &ia32_registers[REG_EAX];
 
 		be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
 	}
@@ -2111,9 +2110,9 @@ static int ia32_register_saved_by(const arch_register_t *reg, int callee)
 		} else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
 			/* all XMM registers are caller save */
 			return reg->index != REG_XMM_NOREG;
-		} else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
-			/* all VFP registers are caller save */
-			return reg->index != REG_VFP_NOREG;
+		} else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_fp]) {
+			/* all FP registers are caller save */
+			return reg->index != REG_FP_NOREG;
 		}
 	}
 	return 0;

ir/be/ia32/bearch_ia32_t.h

@@ -47,11 +47,11 @@ typedef struct ia32_irn_ops_t        ia32_irn_ops_t;
 typedef struct ia32_intrinsic_env_t  ia32_intrinsic_env_t;
 
 typedef struct ia32_irg_data_t {
-	ir_node  **blk_sched;    /**< an array containing the scheduled blocks */
-	unsigned do_x87_sim:1;   /**< set to 1 if x87 simulation should be enforced */
-	unsigned dump:1;         /**< set to 1 if graphs should be dumped */
+	ir_node  **blk_sched;     /**< an array containing the scheduled blocks */
+	unsigned do_x87_sim:1;    /**< set to 1 if x87 simulation should be enforced */
+	unsigned dump:1;          /**< set to 1 if graphs should be dumped */
 	ir_node  *noreg_gp;       /**< unique NoReg_GP node */
-	ir_node  *noreg_vfp;      /**< unique NoReg_VFP node */
+	ir_node  *noreg_fp;       /**< unique NoReg_FP node */
 	ir_node  *noreg_xmm;      /**< unique NoReg_XMM node */
 
 	ir_node  *fpu_trunc_mode; /**< truncate fpu mode */
@@ -111,7 +111,7 @@ static inline ia32_irg_data_t *ia32_get_irg_data(const ir_graph *irg)
  */
 ir_node *ia32_new_NoReg_gp(ir_graph *irg);
 ir_node *ia32_new_NoReg_xmm(ir_graph *irg);
-ir_node *ia32_new_NoReg_vfp(ir_graph *irg);
+ir_node *ia32_new_NoReg_fp(ir_graph *irg);
 
 /**
  * Returns the unique per irg FPU truncation mode node.

ir/be/ia32/ia32_common_transform.c

@@ -271,9 +271,9 @@ static void parse_asm_constraints(constraint_t *constraint, const char *c,
 		case 't':
 		case 'u':
 			/* TODO: mark values so the x87 simulator knows about t and u */
-			if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
+			if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_fp])
 				panic("multiple register classes not supported");
-			cls                   = &ia32_reg_classes[CLASS_ia32_vfp];
+			cls                   = &ia32_reg_classes[CLASS_ia32_fp];
 			all_registers_allowed = 1;
 			break;
 
@@ -753,7 +753,7 @@ ir_node *ia32_gen_Unknown(ir_node *node)
 		if (ia32_cg_config.use_sse2) {
 			res = new_bd_ia32_xUnknown(dbgi, block);
 		} else {
-			res = new_bd_ia32_vfldz(dbgi, block);
+			res = new_bd_ia32_fldz(dbgi, block);
 		}
 	} else if (ia32_mode_needs_gp_reg(mode)) {
 		res = new_bd_ia32_Unknown(dbgi, block);

ir/be/ia32/ia32_emitter.c

@@ -1235,8 +1235,8 @@ static void Copy_emitter(const ir_node *node, const ir_node *op)
 	if (in == out) {
 		return;
 	}
-	/* copies of vf nodes aren't real... */
-	if (in->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
+	/* copies of fp nodes aren't real... */
+	if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
 		return;
 
 	ia32_emitf(node, "movl %R, %R", in, out);
@@ -1271,9 +1271,7 @@ static void emit_be_Perm(const ir_node *node)
 		ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
 		ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
 		ia32_emitf(node, "xorpd %R, %R", in1, in0);
-	} else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
-		/* is a NOP */
-	} else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
+	} else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
 		/* is a NOP */
 	} else {
 		panic("unexpected register class in be_Perm (%+F)", node);
@@ -2225,8 +2223,8 @@ static void bemit_copy(const ir_node *copy)
 
 	if (in == out)
 		return;
-	/* copies of vf nodes aren't real... */
-	if (in->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
+	/* copies of fp nodes aren't real... */
+	if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
 		return;
 
 	assert(in->reg_class == &ia32_reg_classes[CLASS_ia32_gp]);
@@ -2256,9 +2254,7 @@ static void bemit_perm(const ir_node *node)
 		//ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
 		//ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
 		//ia32_emitf(node, "xorpd %R, %R", in1, in0);
-	} else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
-		/* is a NOP */
-	} else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
+	} else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
 		/* is a NOP */
 	} else {
 		panic("unexpected register class in be_Perm (%+F)", node);

ir/be/ia32/ia32_spec.pl

@@ -52,29 +52,18 @@ $state       =  8; # register represents a state
 		{ name => "xmm_NOREG", type => $ignore | $virtual },     # we need a dummy register for NoReg nodes
 		{ mode => $mode_xmm }
 	],
-	vfp => [
-		{ name => "vf0" },
-		{ name => "vf1" },
-		{ name => "vf2" },
-		{ name => "vf3" },
-		{ name => "vf4" },
-		{ name => "vf5" },
-		{ name => "vf6" },
-		{ name => "vf7" },
-		{ name => "vfp_NOREG", type => $ignore | $arbitrary | $virtual }, # we need a dummy register for NoReg nodes
+	fp => [
+		{ name => "st0", realname => "st",    dwarf => 11 },
+		{ name => "st1", realname => "st(1)", dwarf => 12 },
+		{ name => "st2", realname => "st(2)", dwarf => 13 },
+		{ name => "st3", realname => "st(3)", dwarf => 14 },
+		{ name => "st4", realname => "st(4)", dwarf => 15 },
+		{ name => "st5", realname => "st(5)", dwarf => 16 },
+		{ name => "st6", realname => "st(6)", dwarf => 17 },
+		{ name => "st7", realname => "st(7)", dwarf => 18 },
+		{ name => "fp_NOREG", type => $ignore | $arbitrary | $virtual }, # we need a dummy register for NoReg nodes
 		{ mode => $mode_fp87 }
 	],
-	st => [
-		{ name => "st0", realname => "st",    dwarf => 11, type => $ignore },
-		{ name => "st1", realname => "st(1)", dwarf => 12, type => $ignore },
-		{ name => "st2", realname => "st(2)", dwarf => 13, type => $ignore },
-		{ name => "st3", realname => "st(3)", dwarf => 14, type => $ignore },
-		{ name => "st4", realname => "st(4)", dwarf => 15, type => $ignore },
-		{ name => "st5", realname => "st(5)", dwarf => 16, type => $ignore },
-		{ name => "st6", realname => "st(6)", dwarf => 17, type => $ignore },
-		{ name => "st7", realname => "st(7)", dwarf => 18, type => $ignore },
-		{ mode => $mode_fp87, flags => "manual_ra" }
-	],
 	fp_cw => [	# the floating point control word
 		{ name => "fpcw", dwarf => 37, type => $ignore | $state },
 		{ mode => $mode_fpcw, flags => "manual_ra|state" }
@@ -1078,11 +1067,11 @@ NoReg_GP => {
 	mode      => $mode_gp
 },
 
-NoReg_VFP => {
+NoReg_FP => {
 	state     => "pinned",
 	op_flags  => [ "constlike", "dump_noblock" ],
 	irn_flags => [ "not_scheduled" ],
-	reg_req   => { out => [ "vfp_NOREG:I" ] },
+	reg_req   => { out => [ "fp_NOREG:I" ] },
 	units     => [],
 	emit      => "",
 	mode      => $mode_fp87,
@@ -1399,10 +1388,10 @@ Call => {
 	state     => "exc_pinned",
 	reg_req   => {
 		in  => [ "gp", "gp", "none", "gp", "esp", "fpcw", "eax", "ecx", "edx" ],
-		out => [ "esp:I|S", "fpcw:I", "none", "eax", "ecx", "edx", "vf0", "vf1", "vf2", "vf3", "vf4", "vf5", "vf6", "vf7", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "none", "none" ]
+		out => [ "esp:I|S", "fpcw:I", "none", "eax", "ecx", "edx", "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "none", "none" ]
 	},
 	ins       => [ "base", "index", "mem", "addr", "stack", "fpcw", "eax", "ecx", "edx" ],
-	outs      => [ "stack", "fpcw", "M", "eax", "ecx", "edx", "vf0", "vf1", "vf2", "vf3", "vf4", "vf5", "vf6", "vf7", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "X_regular", "X_except" ],
+	outs      => [ "stack", "fpcw", "M", "eax", "ecx", "edx", "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "X_regular", "X_except" ],
 	emit      => "call %*AS3",
 	attr_type => "ia32_call_attr_t",
 	attr      => "unsigned pop, ir_type *call_tp",
@@ -2000,13 +1989,14 @@ Conv_FP2FP => {
 # rematerialisation disabled for all float nodes for now, because the fpcw
 # handler runs before spilling and we might end up with wrong fpcw then
 
-vfadd => {
+fadd => {
 #	irn_flags => [ "rematerializable" ],
 	state     => "exc_pinned",
-	reg_req   => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ],
-	               out => [ "vfp", "none", "none" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "fp", "fp", "fpcw" ],
+	               out => [ "fp", "none", "none" ] },
 	ins       => [ "base", "index", "mem", "left", "right", "fpcw" ],
 	outs      => [ "res", "dummy", "M" ],
+	emit      => 'fadd%FP%FM %AF',
 	am        => "source,binary",
 	latency   => 4,
 	units     => [ "VFP" ],
@@ -2014,13 +2004,14 @@ vfadd => {
 	attr_type => "ia32_x87_attr_t",
 },
 
-vfmul => {
+fmul => {
 #	irn_flags => [ "rematerializable" ],
 	state     => "exc_pinned",
-	reg_req   => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ],
-	               out => [ "vfp", "none", "none" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "fp", "fp", "fpcw" ],
+	               out => [ "fp", "none", "none" ] },
 	ins       => [ "base", "index", "mem", "left", "right", "fpcw" ],
 	outs      => [ "res", "dummy", "M" ],
+	emit      => 'fmul%FP%FM %AF',
 	am        => "source,binary",
 	latency   => 4,
 	units     => [ "VFP" ],
@@ -2028,13 +2019,14 @@ vfmul => {
 	attr_type => "ia32_x87_attr_t",
 },
 
-vfsub => {
+fsub => {
 #	irn_flags => [ "rematerializable" ],
 	state     => "exc_pinned",
-	reg_req   => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ],
-	               out => [ "vfp", "none", "none" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "fp", "fp", "fpcw" ],
+	               out => [ "fp", "none", "none" ] },
 	ins       => [ "base", "index", "mem", "minuend", "subtrahend", "fpcw" ],
 	outs      => [ "res", "dummy", "M" ],
+	emit      => 'fsub%FR%FP%FM %AF',
 	am        => "source,binary",
 	latency   => 4,
 	units     => [ "VFP" ],
@@ -2042,40 +2034,44 @@ vfsub => {
 	attr_type => "ia32_x87_attr_t",
 },
 
-vfdiv => {
+fdiv => {
 	state     => "exc_pinned",
-	reg_req   => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ],
-	               out => [ "vfp", "none", "none" ] },
+	reg_req   => { in => [ "gp", "gp", "none", "fp", "fp", "fpcw" ],
+	               out => [ "fp", "none", "none" ] },
 	ins       => [ "base", "index", "mem", "dividend", "divisor", "fpcw" ],
 	outs      => [ "res", "dummy", "M" ],
+	emit      => 'fdiv%FR%FP%FM %AF',
 	am        => "source,binary",
 	latency   => 20,
 	units     => [ "VFP" ],
 	attr_type => "ia32_x87_attr_t",
 },
 
-vfprem => {
-	reg_req   => { in => [ "vfp", "vfp", "fpcw" ], out => [ "vfp" ] },
+fprem => {
+	reg_req   => { in => [ "fp", "fp", "fpcw" ], out => [ "fp" ] },
 	ins       => [ "left", "right", "fpcw" ],
+	emit      => 'fprem1',
 	latency   => 20,
 	units     => [ "VFP" ],
 	mode      => $mode_fp87,
 	attr_type => "ia32_x87_attr_t",
 },
 
-vfabs => {
+fabs => {
 	irn_flags => [ "rematerializable" ],
-	reg_req   => { in => [ "vfp"], out => [ "vfp" ] },
+	reg_req   => { in => [ "fp"], out => [ "fp" ] },
 	ins       => [ "value" ],
+	emit      => 'fabs',
 	latency   => 2,
 	units     => [ "VFP" ],
 	mode      => $mode_fp87,
 	attr_type => "ia32_x87_attr_t",
 },
 
-vfchs => {
+fchs => {
 	irn_flags => [ "rematerializable" ],
-	reg_req   => { in => [ "vfp"], out => [ "vfp" ] },
+	reg_req   => { in => [ "fp"], out => [ "fp" ] },
+	emit      => 'fchs',
 	ins       => [ "value" ],
 	latency   => 2,
 	units     => [ "VFP" ],
@@ -2083,14 +2079,15 @@ vfchs => {
 	attr_type => "ia32_x87_attr_t",
 },
 
-vfld => {
+fld => {
 	irn_flags => [ "rematerializable" ],
 	op_flags  => [ "uses_memory", "fragile" ],
 	state     => "exc_pinned",
 	reg_req   => { in => [ "gp", "gp", "none" ],
-	               out => [ "vfp", "none", "none", "none", "none" ] },
+	               out => [ "fp", "none", "none", "none", "none" ] },
 	ins       => [ "base", "index", "mem" ],
 	outs      => [ "res", "unused", "M", "X_regular", "X_except" ],
+	emit      => 'fld%FM %AM',
 	attr      => "ir_mode *load_mode",
 	init_attr => "attr->attr.ls_mode = load_mode;",
 	latency   => 2,
@@ -2098,14 +2095,15 @@ vfld => {
 	attr_type => "ia32_x87_attr_t",
 },
 
-vfst => {
+fst => {
 	irn_flags => [ "rematerializable" ],
 	op_flags  => [ "uses_memory", "fragile" ],
 	state     => "exc_pinned",
-	reg_req   => { in => [ "gp", "gp", "none", "vfp" ],
+	reg_req   => { in => [ "gp", "gp", "none", "fp" ],
 	               out => [ "none", "none", "none" ] },
 	ins       => [ "base", "index", "mem", "val" ],
 	outs      => [ "M", "X_regular", "X_except" ],
+	emit      => 'fst%FP%FM %AM',
 	attr      => "ir_mode *store_mode",
 	init_attr => "attr->attr.ls_mode = store_mode;",
 	latency   => 2,
@@ -2113,85 +2111,93 @@ vfst => {
 	attr_type => "ia32_x87_attr_t",
 },
 
-vfild => {
+fild => {
 	state     => "exc_pinned",
 	reg_req   => { in => [ "gp", "gp", "none" ],
-	               out => [ "vfp", "none", "none" ] },
+	               out => [ "fp", "none", "none" ] },
 	outs      => [ "res", "unused", "M" ],
 	ins       => [ "base", "index", "mem" ],
+	emit      => 'fild%FM %AM',
 	latency   => 4,
 	units     => [ "VFP" ],
 	attr_type => "ia32_x87_attr_t",
 },
 
-vfist => {
+fist => {
 	op_flags  => [ "uses_memory", "fragile" ],
 	state     => "exc_pinned",
-	reg_req   => { in => [ "gp", "gp", "none", "vfp", "fpcw" ],
+	reg_req   => { in => [ "gp", "gp", "none", "fp", "fpcw" ],
 	               out => [ "none", "none", "none", "none" ] },
 	ins       => [ "base", "index", "mem", "val", "fpcw" ],
 	outs      => [ "dummy", "M", "X_regular", "X_except" ],
+	emit      => 'fist%FP%FM %AM',
 	latency   => 4,
 	units     => [ "VFP" ],
 	attr_type => "ia32_x87_attr_t",
 },
 
 # SSE3 fisttp instruction
-vfisttp => {
+fisttp => {
 	op_flags  => [ "uses_memory", "fragile" ],
 	state     => "exc_pinned",
-	reg_req   => { in => [ "gp", "gp", "none", "vfp" ],
+	reg_req   => { in => [ "gp", "gp", "none", "fp" ],
 	               out => [ "in_r4", "none", "none", "none" ]},
 	ins       => [ "base", "index", "mem", "val" ],
 	outs      => [ "res", "M", "X_regular", "X_except" ],
+	emit      => 'fisttp%FM %AM',
 	latency   => 4,
 	units     => [ "VFP" ],
 	attr_type => "ia32_x87_attr_t",
 },
 
-vfldz => {
+fldz => {
 	irn_flags => [ "rematerializable" ],
-	reg_req   => { out => [ "vfp" ] },
+	reg_req   => { out => [ "fp" ] },
 	outs      => [ "res" ],
+	emit      => 'fldz',
 	latency   => 4,
 	units     => [ "VFP" ],
 	mode      => $mode_fp87,
 	attr_type => "ia32_x87_attr_t",
 },
 
-vfld1 => {
+fld1 => {
 	irn_flags => [ "rematerializable" ],
-	reg_req   => { out => [ "vfp" ] },
+	reg_req   => { out => [ "fp" ] },
 	outs      => [ "res" ],
+	emit      => 'fld1',
 	latency   => 4,
 	units     => [ "VFP" ],
 	mode      => $mode_fp87,
 	attr_type => "ia32_x87_attr_t",
 },
 
-vfldpi => {
+fldpi => {
 	irn_flags => [ "rematerializable" ],
-	reg_req   => { out => [ "vfp" ] },
+	reg_req   => { out => [ "fp" ] },
 	outs      => [ "res" ],
+	emit      => 'fldpi',
 	latency   => 4,
 	units     => [ "VFP" ],
 	mode      => $mode_fp87,
 	attr_type => "ia32_x87_attr_t",
 },
 
-vfldln2 => {
+fldln2 => {
 	irn_flags => [ "rematerializable" ],
-	reg_req   => { out => [ "vfp" ] },
+	reg_req   => { out => [ "fp" ] },
 	outs      => [ "res" ],
+	emit      => 'fldln2',
 	latency   => 4,
 	units     => [ "VFP" ],
 	mode      => $mode_fp87,
 	attr_type => "ia32_x87_attr_t",
 },
 
-vfldlg2 => {
+fldlg2 => {
 	irn_flags => [ "rematerializable" ],
-	reg_req   => { out => [ "vfp" ] },
+	reg_req   => { out => [ "fp" ] },
+	emit      => 'fldlg2',
 	outs      => [ "res" ],
 	latency   => 4,
 	units     => [ "VFP" ],
@@ -2199,9 +2205,10 @@ vfldlg2 => {
 	attr_type => "ia32_x87_attr_t",
 },
 
-vfldl2t => {
+fldl2t => {
 	irn_flags => [ "rematerializable" ],
-	reg_req   => { out => [ "vfp" ] },
+	reg_req   => { out => [ "fp" ] },
+	emit      => 'fldll2t',
 	outs      => [ "res" ],
 	latency   => 4,
 	units     => [ "VFP" ],
@@ -2209,9 +2216,10 @@ vfldl2t => {
 	attr_type => "ia32_x87_attr_t",
 },
 
-vfldl2e => {
+fldl2e => {
 	irn_flags => [ "rematerializable" ],
-	reg_req   => { out => [ "vfp" ] },
+	reg_req   => { out => [ "fp" ] },
+	emit      => 'fldl2e',
 	outs      => [ "res" ],
 	latency   => 4,
 	units     => [ "VFP" ],
@@ -2219,13 +2227,32 @@ vfldl2e => {
 	attr_type => "ia32_x87_attr_t",
 },
 
-vFucomFnstsw => {
+FucomFnstsw => {
+# we can't allow to rematerialize this node so we don't
+#  accidently produce Phi(Fucom, Fucom(ins_permuted))
+#	irn_flags => [ "rematerializable" ],
+	reg_req   => { in => [ "fp", "fp" ], out => [ "eax" ] },
+	ins       => [ "left", "right" ],
+	outs      => [ "flags" ],
+	emit      => "fucom%FP %F0\n".
+	             "fnstsw %%ax",
+	attr      => "bool ins_permuted",
+	init_attr => "attr->attr.data.ins_permuted = ins_permuted;",
+	latency   => 3,
+	units     => [ "VFP" ],
+	attr_type => "ia32_x87_attr_t",
+	mode      => $mode_gp
+},
+
+FucomppFnstsw => {
 # we can't allow to rematerialize this node so we don't
 #  accidently produce Phi(Fucom, Fucom(ins_permuted))
 #	irn_flags => [ "rematerializable" ],
-	reg_req   => { in => [ "vfp", "vfp" ], out => [ "eax" ] },
+	reg_req   => { in => [ "fp", "fp" ], out => [ "eax" ] },
 	ins       => [ "left", "right" ],
 	outs      => [ "flags" ],
+	emit      => "fucom%FP %F0\n".
+	             "fnstsw %%ax",
 	attr      => "bool ins_permuted",
 	init_attr => "attr->attr.data.ins_permuted = ins_permuted;",
 	latency   => 3,
@@ -2234,11 +2261,12 @@ vFucomFnstsw => {
 	mode      => $mode_gp
 },
 
-vFucomi => {
+Fucomi => {
 	irn_flags => [ "rematerializable" ],
-	reg_req   => { in => [ "vfp", "vfp" ], out => [ "eflags" ] },
+	reg_req   => { in => [ "fp", "fp" ], out => [ "eflags" ] },
 	ins       => [ "left", "right" ],
 	outs      => [ "flags" ],
+	emit      => 'fucom%FPi %F0',
 	attr      => "bool ins_permuted",
 	init_attr => "attr->attr.data.ins_permuted = ins_permuted;",
 	latency   => 3,
@@ -2247,11 +2275,13 @@ vFucomi => {
 	mode      => $mode_gp
 },
 
-vFtstFnstsw => {
+FtstFnstsw => {
 #	irn_flags => [ "rematerializable" ],
-	reg_req   => { in => [ "vfp" ], out => [ "eax" ] },
+	reg_req   => { in => [ "fp" ], out => [ "eax" ] },
 	ins       => [ "left" ],
 	outs      => [ "flags" ],
+	emit      => "ftst\n".
+	             "fnstsw %%ax",
 	attr      => "bool ins_permuted",
 	init_attr => "attr->attr.data.ins_permuted = ins_permuted;",
 	latency   => 3,
@@ -2271,170 +2301,6 @@ Sahf => {
 	mode      => $mode_flags,
 },
 
-fadd => {
-	state     => "exc_pinned",
-	emit      => 'fadd%FP%FM %AF',
-	latency   => 4,
-	attr_type => "ia32_x87_attr_t",