Commit bdf3df76 authored by Christian Würdig's avatar Christian Würdig
Browse files

removed union from register requirements to make static inits easier

parent 504619ba
......@@ -102,7 +102,7 @@ int arch_get_allocatable_regs(const arch_env_t *env, const ir_node *irn,
return req->cls->n_regs;
case arch_register_req_type_limited:
return req->data.limited(irn, pos, bs);
return req->limited(irn, pos, bs);
default:
assert(0 && "This register requirement case is not covered");
......@@ -136,7 +136,7 @@ int arch_reg_is_allocatable(const arch_env_t *env, const ir_node *irn,
case arch_register_req_type_limited:
{
bitset_t *bs = bitset_alloca(req.cls->n_regs);
req.data.limited(irn, pos, bs);
req.limited(irn, pos, bs);
res = bitset_is_set(bs, arch_register_get_index(reg));
}
break;
......
......@@ -170,11 +170,10 @@ typedef enum _arch_register_req_type_t {
* Expresses requirements to register allocation for an operand.
*/
typedef struct _arch_register_req_t {
arch_register_req_type_t type; /**< The type of the constraint. */
const arch_register_class_t *cls; /**< The register class this
arch_register_req_type_t type; /**< The type of the constraint. */
const arch_register_class_t *cls; /**< The register class this
constraint belongs to. */
union {
int (*limited)(const ir_node *irn, int pos, bitset_t *bs);
int (*limited)(const ir_node *irn, int pos, bitset_t *bs);
/**< In case of the 'limited'
constraint, this function
must put all allowable
......@@ -182,12 +181,11 @@ typedef struct _arch_register_req_t {
return the number of registers
in the bitset. */
int pos; /**< In case of the equal constraint,
int pos; /**< In case of the equal constraint,
this gives the position of the
operand to which the register of
this should be equal to. Same for
unequal. */
} data;
} arch_register_req_t;
/**
......
......@@ -177,7 +177,7 @@ static int try_pre_color(be_chordal_env_t *env, ir_node *irn,
const arch_register_t *reg;
int col;
req.data.limited(irn, -1, bs);
req.limited(irn, -1, bs);
col = bitset_next_set(bs, 0);
reg = arch_register_for_index(env->cls, col);
......
......@@ -197,7 +197,7 @@ static void co_collect_units(ir_node *irn, void *env) {
/* Src == Tgt of a 2-addr-code instruction */
if (is_2addr_code(get_arch_env(co), irn, &req)) {
int pos = req.data.pos;
int pos = req.pos;
ir_node *other = get_irn_n(irn, pos);
if (!nodes_interfere(co->chordal_env, irn, other)) {
unit->nodes = xmalloc(2 * sizeof(*unit->nodes));
......@@ -278,7 +278,7 @@ int is_optimizable_arg(const copy_opt_t *co, ir_node *irn) {
arch_get_register_req(aenv, &req, n, -1);
if( ( (req.type == arch_register_req_type_should_be_same && get_irn_n(n, req.data.pos) == irn) ||
if( ( (req.type == arch_register_req_type_should_be_same && get_irn_n(n, req.pos) == irn) ||
is_Reg_Phi(n) ||
is_Perm(get_arch_env(co), n)
) && (irn == n || !nodes_interfere(co->chordal_env, irn, n)))
......
......@@ -72,7 +72,7 @@ static unsigned dump_flags = DUMP_INITIAL | DUMP_SCHED | DUMP_PREPARED | DUMP_RA
static const be_ra_t *ra = &be_ra_chordal_allocator;
/* back end instruction set architecture to use */
static const arch_isa_if_t *isa_if = &firm_isa;
static const arch_isa_if_t *isa_if = &ia32_isa_if;
#ifdef WITH_LIBCORE
......
......@@ -199,7 +199,8 @@ static const arch_register_class_t *firm_get_reg_class(const void *self, int i)
static const arch_register_req_t firm_std_reg_req = {
arch_register_req_type_normal,
&reg_classes[CLS_DATAB],
{ NULL }
NULL,
0
};
static const arch_register_req_t *
......
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