Commit c8b47452 authored by Christoph Mallon's avatar Christoph Mallon
Browse files

Build immediates for 64bit subs.

[r15727]
parent 0fb75657
......@@ -608,8 +608,8 @@ Sub64Bit => {
emit => '
. movl %S0, %D0
. movl %S1, %D1
. subl %S2, %D0
. sbbl %S3, %D1
. subl %SI2, %D0
. sbbl %SI3, %D1
',
outs => [ "low_res", "high_res" ],
units => [ "GP" ],
......
......@@ -3759,6 +3759,20 @@ static ir_node *gen_ia32_Add64Bit(ir_node *node)
return new_op;
}
static ir_node *gen_ia32_Sub64Bit(ir_node *node)
{
ir_node *a_l = be_transform_node(get_irn_n(node, 0));
ir_node *a_h = be_transform_node(get_irn_n(node, 1));
ir_node *b_l = create_immediate_or_transform(get_irn_n(node, 2), 0);
ir_node *b_h = create_immediate_or_transform(get_irn_n(node, 3), 0);
ir_node *block = be_transform_node(get_nodes_block(node));
dbg_info *dbgi = get_irn_dbg_info(node);
ir_graph *irg = current_ir_graph;
ir_node *new_op = new_rd_ia32_Sub64Bit(dbgi, irg, block, a_l, a_h, b_l, b_h);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
return new_op;
}
/**
* Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
* op1 - target to be shifted
......@@ -4441,6 +4455,7 @@ static void register_transformers(void)
/* transform ops from intrinsic lowering */
GEN(ia32_Add64Bit);
GEN(ia32_Sub64Bit);
GEN(ia32_l_Add);
GEN(ia32_l_Adc);
GEN(ia32_l_Sub);
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment