normalise Or/Eor => Add where possible

ir/ir/iropt.c

@@ -1984,7 +1984,6 @@ static ir_node *transform_node_Add(ir_node *n)
 {
 	ir_mode *mode;
 	ir_node *a, *b, *c, *oldn = n;
-	vrp_attr *a_vrp, *b_vrp;
 
 	n = transform_node_AddSub(n);
 
@@ -2064,17 +2063,6 @@ static ir_node *transform_node_Add(ir_node *n)
 		}
 	}
 
-	a_vrp = vrp_get_info(a);
-	b_vrp = vrp_get_info(b);
-
-	if (a_vrp && b_vrp) {
-		ir_tarval *vrp_val = tarval_and(a_vrp->bits_not_set, b_vrp->bits_not_set);
-
-		if (tarval_is_null(vrp_val)) {
-			dbg_info *dbgi  = get_irn_dbg_info(n);
-			return new_rd_Or(dbgi, get_nodes_block(n), a, b, mode);
-		}
-	}
 	return n;
 }  /* transform_node_Add */
 
@@ -3417,6 +3405,19 @@ static ir_node *transform_node_Eor(ir_node *n)
 		return n;
 	}
 
+	if (mode_is_int(mode)) {
+		vrp_attr *a_vrp = vrp_get_info(a);
+		vrp_attr *b_vrp = vrp_get_info(b);
+		if (a_vrp != NULL && b_vrp != NULL) {
+			ir_tarval *vrp_val = tarval_and(a_vrp->bits_not_set, b_vrp->bits_not_set);
+
+			if (tarval_is_null(vrp_val)) {
+				dbg_info *dbgi = get_irn_dbg_info(n);
+				return new_rd_Add(dbgi, get_nodes_block(n), a, b, mode);
+			}
+		}
+	}
+
 	n = transform_bitwise_distributive(n, transform_node_Eor);
 	if (is_Eor(n))
 		n = transform_node_bitop_shift(n);
@@ -5078,6 +5079,21 @@ static ir_node *transform_node_Or(ir_node *n)
 	n = transform_bitwise_distributive(n, transform_node_Or);
 	if (is_Or(n))
 		n = transform_node_bitop_shift(n);
+	if (n != oldn)
+		return n;
+
+	if (mode_is_int(mode)) {
+		vrp_attr *a_vrp = vrp_get_info(a);
+		vrp_attr *b_vrp = vrp_get_info(b);
+		if (a_vrp != NULL && b_vrp != NULL) {
+			ir_tarval *vrp_val = tarval_and(a_vrp->bits_not_set, b_vrp->bits_not_set);
+
+			if (tarval_is_null(vrp_val)) {
+				dbg_info *dbgi = get_irn_dbg_info(n);
+				return new_rd_Add(dbgi, get_nodes_block(n), a, b, mode);
+			}
+		}
+	}
 
 	return n;
 }  /* transform_node_Or */

ir/opt/fp-vrp.c

@@ -745,6 +745,28 @@ exchange_only:
 			break;
 		}
 
+		case iro_Eor: {
+			ir_node*       const l  = get_Eor_left(irn);
+			ir_node*       const r  = get_Eor_right(irn);
+			bitinfo const* const bl = get_bitinfo(l);
+			bitinfo const* const br = get_bitinfo(r);
+			/* if each bit is guaranteed to be zero on either the left or right
+			 * then an Add will have the same effect as the Eor. Change it for
+			 * normalisation */
+			if (tarval_is_null(tarval_and(bl->z, br->z))) {
+				dbg_info      *dbgi     = get_irn_dbg_info(irn);
+				ir_node       *block    = get_nodes_block(irn);
+				ir_mode       *mode     = get_irn_mode(irn);
+				ir_node       *new_node = new_rd_Add(dbgi, block, l, r, mode);
+				bitinfo const *bi       = get_bitinfo(irn);
+				DB((dbg, LEVEL_2, "%+F(%+F, %+F) normalised to Add\n", irn, l, r));
+				set_bitinfo(new_node, bi->z, bi->o);
+				exchange(irn, new_node);
+				env->modified = 1;
+			}
+			break;
+		}
+
 		case iro_Or: {
 			ir_node*       const l  = get_Or_left(irn);
 			ir_node*       const r  = get_Or_right(irn);
@@ -763,6 +785,22 @@ exchange_only:
 					env->modified = 1;
 				}
 			}
+
+			/* if each bit is guaranteed to be zero on either the left or right
+			 * then an Add will have the same effect as the Or. Change it for
+			 * normalisation */
+			if (tarval_is_null(tarval_and(bl->z, br->z))) {
+				dbg_info      *dbgi     = get_irn_dbg_info(irn);
+				ir_node       *block    = get_nodes_block(irn);
+				ir_mode       *mode     = get_irn_mode(irn);
+				ir_node       *new_node = new_rd_Add(dbgi, block, l, r, mode);
+				bitinfo const *bi       = get_bitinfo(irn);
+				DB((dbg, LEVEL_2, "%+F(%+F, %+F) normalised to Add\n", irn, l, r));
+				set_bitinfo(new_node, bi->z, bi->o);
+				exchange(irn, new_node);
+				env->modified = 1;
+			}
+
 			break;
 		}
 	}