Commit cbcf8b93 authored by Christoph Mallon's avatar Christoph Mallon
Browse files

Remove final \n from panic messages, panic() adds a newline automagically.

[r21362]
parent d7ec9df3
......@@ -969,7 +969,7 @@ static void emit_arm_fpaDbl2GP(const ir_node *irn) {
static void emit_arm_LdTls(const ir_node *irn) {
(void) irn;
panic("TLS not supported for this target\n");
panic("TLS not supported for this target");
/* Er... our gcc does not support it... Install a newer toolchain. */
}
......
......@@ -224,11 +224,11 @@ static ir_node *gen_Conv(ir_node *node) {
}
}
else if (USE_VFP(env_cg->isa)) {
panic("VFP not supported yet\n");
panic("VFP not supported yet");
return NULL;
}
else {
panic("Softfloat not supported yet\n");
panic("Softfloat not supported yet");
return NULL;
}
}
......@@ -264,7 +264,7 @@ static ir_node *gen_Conv(ir_node *node) {
return gen_zero_extension(dbg, block, new_op, min_bits);
}
} else {
panic("Cannot handle Conv %+F->%+F with %d->%d bits\n", src_mode, dst_mode,
panic("Cannot handle Conv %+F->%+F with %d->%d bits", src_mode, dst_mode,
src_bits, dst_bits);
return NULL;
}
......@@ -317,11 +317,11 @@ static ir_node *gen_Add(ir_node *node) {
return new_rd_arm_fpaAdf(dbg, irg, block, new_op1, new_op2, mode);
} else if (USE_VFP(env_cg->isa)) {
assert(mode != mode_E && "IEEE Extended FP not supported");
panic("VFP not supported yet\n");
panic("VFP not supported yet");
return NULL;
}
else {
panic("Softfloat not supported yet\n");
panic("Softfloat not supported yet");
return NULL;
}
} else {
......@@ -393,11 +393,11 @@ static ir_node *gen_Mul(ir_node *node) {
}
else if (USE_VFP(env_cg->isa)) {
assert(mode != mode_E && "IEEE Extended FP not supported");
panic("VFP not supported yet\n");
panic("VFP not supported yet");
return NULL;
}
else {
panic("Softfloat not supported yet\n");
panic("Softfloat not supported yet");
return NULL;
}
}
......@@ -432,10 +432,10 @@ static ir_node *gen_Quot(ir_node *node) {
return new_rd_arm_fpaDvf(dbg, current_ir_graph, block, new_op1, new_op2, mode);
} else if (USE_VFP(env_cg->isa)) {
assert(mode != mode_E && "IEEE Extended FP not supported");
panic("VFP not supported yet\n");
panic("VFP not supported yet");
}
else {
panic("Softfloat not supported yet\n");
panic("Softfloat not supported yet");
return NULL;
}
}
......@@ -526,11 +526,11 @@ static ir_node *gen_Sub(ir_node *node) {
return new_rd_arm_fpaSuf(dbg, irg, block, new_op1, new_op2, mode);
} else if (USE_VFP(env_cg->isa)) {
assert(mode != mode_E && "IEEE Extended FP not supported");
panic("VFP not supported yet\n");
panic("VFP not supported yet");
return NULL;
}
else {
panic("Softfloat not supported yet\n");
panic("Softfloat not supported yet");
return NULL;
}
}
......@@ -759,10 +759,10 @@ static ir_node *gen_Abs(ir_node *node) {
return new_rd_arm_fpaAbs(dbg, current_ir_graph, block, new_op, mode);
else if (USE_VFP(env_cg->isa)) {
assert(mode != mode_E && "IEEE Extended FP not supported");
panic("VFP not supported yet\n");
panic("VFP not supported yet");
}
else {
panic("Softfloat not supported yet\n");
panic("Softfloat not supported yet");
}
}
assert(mode_is_data(mode));
......@@ -788,10 +788,10 @@ static ir_node *gen_Minus(ir_node *node) {
return new_rd_arm_fpaMvf(dbg, current_ir_graph, block, op, mode);
else if (USE_VFP(env_cg->isa)) {
assert(mode != mode_E && "IEEE Extended FP not supported");
panic("VFP not supported yet\n");
panic("VFP not supported yet");
}
else {
panic("Softfloat not supported yet\n");
panic("Softfloat not supported yet");
}
}
assert(mode_is_data(mode));
......@@ -821,10 +821,10 @@ static ir_node *gen_Load(ir_node *node) {
new_load = new_rd_arm_fpaLdf(dbg, irg, block, new_ptr, new_mem, mode);
else if (USE_VFP(env_cg->isa)) {
assert(mode != mode_E && "IEEE Extended FP not supported");
panic("VFP not supported yet\n");
panic("VFP not supported yet");
}
else {
panic("Softfloat not supported yet\n");
panic("Softfloat not supported yet");
}
}
else {
......@@ -843,7 +843,7 @@ static ir_node *gen_Load(ir_node *node) {
new_load = new_rd_arm_Load(dbg, irg, block, new_ptr, new_mem);
break;
default:
panic("mode size not supported\n");
panic("mode size not supported");
}
} else {
/* zero extended loads */
......@@ -858,7 +858,7 @@ static ir_node *gen_Load(ir_node *node) {
new_load = new_rd_arm_Load(dbg, irg, block, new_ptr, new_mem);
break;
default:
panic("mode size not supported\n");
panic("mode size not supported");
}
}
}
......@@ -898,9 +898,9 @@ static ir_node *gen_Store(ir_node *node) {
new_store = new_rd_arm_fpaStf(dbg, irg, block, new_ptr, new_val, new_mem, mode);
else if (USE_VFP(env_cg->isa)) {
assert(mode != mode_E && "IEEE Extended FP not supported");
panic("VFP not supported yet\n");
panic("VFP not supported yet");
} else {
panic("Softfloat not supported yet\n");
panic("Softfloat not supported yet");
}
} else {
assert(mode_is_data(mode) && "unsupported mode for Store");
......@@ -1083,10 +1083,10 @@ static ir_node *gen_Const(ir_node *node) {
}
else if (USE_VFP(env_cg->isa)) {
assert(mode != mode_E && "IEEE Extended FP not supported");
panic("VFP not supported yet\n");
panic("VFP not supported yet");
}
else {
panic("Softfloat not supported yet\n");
panic("Softfloat not supported yet");
}
}
return create_const_graph(node, block);
......@@ -1450,7 +1450,7 @@ static ir_node *gen_Proj_be_SubSP(ir_node *node) {
*/
static ir_node *gen_Proj_Cmp(ir_node *node) {
(void) node;
panic("Mux NYI\n");
panic("Mux NYI");
}
......@@ -1619,7 +1619,7 @@ static ir_node *gen_Phi(ir_node *node) {
* the BAD transformer.
*/
static ir_node *bad_transform(ir_node *irn) {
panic("ARM backend: Not implemented: %+F\n", irn);
panic("ARM backend: Not implemented: %+F", irn);
return irn;
}
......
......@@ -273,7 +273,7 @@ static void dump_arith_tarval(tarval *tv, int bytes)
return;
}
panic("Can't dump a tarval with %d bytes\n", bytes);
panic("Can't dump a tarval with %d bytes", bytes);
}
/**
......@@ -495,7 +495,7 @@ static void dump_size_type(size_t size) {
break;
default:
panic("Try to dump a type with %u bytes\n", (unsigned) size);
panic("Try to dump a type with %u bytes", (unsigned)size);
}
}
......@@ -806,7 +806,7 @@ static void dump_bitfield(normal_or_bitfield *vals, size_t offset_bits,
panic("bitfield initializer is compound");
}
if (tv == NULL) {
panic("Couldn't get numeric value for bitfield initializer\n");
panic("Couldn't get numeric value for bitfield initializer");
}
/* normalize offset */
......@@ -1050,7 +1050,7 @@ static void dump_compound_init(be_gas_decl_env_t *env, ir_entity *ent)
tarval *tv = get_atomic_init_tv(value);
unsigned char curr_bits, last_bits = 0;
if (tv == NULL) {
panic("Couldn't get numeric value for bitfield initializer '%s'\n",
panic("Couldn't get numeric value for bitfield initializer '%s'",
get_entity_ld_name(ent));
}
/* normalize offset */
......
......@@ -62,7 +62,7 @@ static void clear_reg_value(ir_node *node)
reg = arch_get_irn_register(arch_env, node);
if(reg == NULL) {
panic("No register assigned at %+F\n", node);
panic("No register assigned at %+F", node);
}
if(arch_register_type_is(reg, virtual))
return;
......@@ -87,7 +87,7 @@ static void set_reg_value(ir_node *node)
reg = arch_get_irn_register(arch_env, node);
if(reg == NULL) {
panic("No register assigned at %+F\n", node);
panic("No register assigned at %+F", node);
}
if(arch_register_type_is(reg, virtual))
return;
......@@ -159,7 +159,7 @@ void be_peephole_before_exchange(const ir_node *old_node, ir_node *new_node)
reg = arch_get_irn_register(arch_env, old_node);
if (reg == NULL) {
panic("No register assigned at %+F\n", old_node);
panic("No register assigned at %+F", old_node);
}
assert(reg == arch_get_irn_register(arch_env, new_node) &&
"KILLING a node and replacing by different register is not allowed");
......
......@@ -215,7 +215,7 @@ static void do_spilling(ir_nodeset_t *live_nodes, ir_node *node)
int is_use;
if (cand_idx >= n_live_nodes) {
panic("can't spill enough values for node %+F\n", node);
panic("can't spill enough values for node %+F", node);
}
......
......@@ -386,7 +386,7 @@ void be_ssa_construction_fix_users_array(be_ssa_construction_env_t *env,
def = search_def(env, at);
if(def == NULL) {
panic("no definition found for %+F at position %d\n", use, pos);
panic("no definition found for %+F at position %d", use, pos);
}
DBG((dbg, LEVEL_2, "\t%+F(%d) -> %+F\n", use, pos, def));
......
......@@ -843,7 +843,7 @@ const arch_register_req_t *parse_clobber(const char *clobber)
unsigned *limited;
if(reg == NULL) {
panic("Register '%s' mentioned in asm clobber is unknown\n", clobber);
panic("Register '%s' mentioned in asm clobber is unknown", clobber);
}
assert(reg->index < 32);
......
......@@ -316,7 +316,7 @@ static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
case 8: be_emit_char('b'); return;
}
}
panic("Can't output mode_suffix for %+F\n", mode);
panic("Can't output mode_suffix for %+F", mode);
}
void ia32_emit_mode_suffix(const ir_node *node)
......@@ -1686,7 +1686,7 @@ static void emit_be_Perm(const ir_node *node)
} else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
/* is a NOP */
} else {
panic("unexpected register class in be_Perm (%+F)\n", node);
panic("unexpected register class in be_Perm (%+F)", node);
}
}
......
......@@ -3995,7 +3995,7 @@ static ir_node *gen_ia32_l_FloattoLL(ir_node *node) {
* the BAD transformer.
*/
static ir_node *bad_transform(ir_node *node) {
panic("No transform function for %+F available.\n", node);
panic("No transform function for %+F available.", node);
return NULL;
}
......
......@@ -236,10 +236,10 @@ static void mips_set_frame_entity(ir_node *node, ir_entity *entity)
mips_load_store_attr_t *attr;
if(!is_mips_irn(node)) {
panic("trying to set frame entity on non load/store node %+F\n", node);
panic("trying to set frame entity on non load/store node %+F", node);
}
if(!mips_is_Load(node) && !mips_is_Store(node)) {
panic("trying to set frame entity on non load/store node %+F\n", node);
panic("trying to set frame entity on non load/store node %+F", node);
}
attr = get_irn_generic_attr(node);
......@@ -255,10 +255,10 @@ static void mips_set_frame_offset(ir_node *node, int offset)
mips_load_store_attr_t *attr;
if(!is_mips_irn(node)) {
panic("trying to set frame offset on non load/store node %+F\n", node);
panic("trying to set frame offset on non load/store node %+F", node);
}
if(!mips_is_Load(node) && !mips_is_Store(node)) {
panic("trying to set frame offset on non load/store node %+F\n", node);
panic("trying to set frame offset on non load/store node %+F", node);
}
attr = get_irn_generic_attr(node);
......
......@@ -317,7 +317,7 @@ void mips_emit_IncSP(const ir_node *node)
}
if(offset > 0xffff || offset < -0xffff) {
panic("stackframe > 2^16 bytes not supported yet\n");
panic("stackframe > 2^16 bytes not supported yet");
}
if(offset > 0) {
......
......@@ -305,7 +305,7 @@ static ir_node* gen_Const(ir_node *node)
if(tarval_is_long(tv)) {
val = get_tarval_long(tv);
} else {
panic("Can't get value of tarval %+F\n", node);
panic("Can't get value of tarval %+F", node);
}
val = get_tarval_long(tv);
......@@ -499,7 +499,7 @@ static ir_node *gen_Proj_DivMod(ir_node *node)
break;
}
panic("invalid proj attached to %+F\n", divmod);
panic("invalid proj attached to %+F", divmod);
}
static ir_node *gen_Proj_Start(ir_node *node)
......@@ -775,7 +775,7 @@ static ir_node *gen_Conv(ir_node *node)
} else if(src_size == 16) {
res = new_rd_mips_seh(dbgi, irg, block, new_op);
} else {
panic("invalid conv %+F\n", node);
panic("invalid conv %+F", node);
}
} else {
ir_node *and_const;
......@@ -785,7 +785,7 @@ static ir_node *gen_Conv(ir_node *node)
} else if(src_size == 16) {
and_const = mips_create_Immediate(0xffff);
} else {
panic("invalid conv %+F\n", node);
panic("invalid conv %+F", node);
}
res = new_rd_mips_and(dbgi, irg, block, new_op, and_const);
}
......@@ -1131,7 +1131,7 @@ static ir_node *gen_AddSP(ir_node *node)
static ir_node *gen_Bad(ir_node *node)
{
panic("Unexpected node %+F found in mips transform phase.\n", node);
panic("Unexpected node %+F found in mips transform phase.", node);
return NULL;
}
......
......@@ -63,7 +63,7 @@ void instrument_initcall(ir_graph *irg, ir_entity *ent) {
}
}
if (first_block == NULL) {
panic("Cannot find first block of irg %+F\n", irg);
panic("Cannot find first block of irg %+F", irg);
}
/* check if this block has only one predecessor */
......
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