Commit ce4f9044 authored by Matthias Braun's avatar Matthias Braun
Browse files

- change float nodes to mode_E

- correctly capture spills and reloads in coalescer code
parent 1b0c9951
...@@ -77,6 +77,7 @@ static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place, ...@@ -77,6 +77,7 @@ static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
{ {
ir_node *block, *res; ir_node *block, *res;
ir_node *startnode; ir_node *startnode;
ir_node *in[1];
if(*place != NULL) if(*place != NULL)
return *place; return *place;
...@@ -87,10 +88,17 @@ static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place, ...@@ -87,10 +88,17 @@ static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
*place = res; *place = res;
startnode = get_irg_start(cg->irg); startnode = get_irg_start(cg->irg);
/* make sure we get scheduled very early... */
add_irn_dep(startnode, res);
/* schedule the node if we already have a schedule program */
if(sched_is_scheduled(startnode)) { if(sched_is_scheduled(startnode)) {
sched_add_before(startnode, res); sched_add_before(startnode, res);
} }
/* keep the node so it isn't accidently removed when unused ... */
in[0] = res;
be_new_Keep(arch_register_get_class(reg), cg->irg, block, 1, in);
return res; return res;
} }
...@@ -758,28 +766,21 @@ static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, in ...@@ -758,28 +766,21 @@ static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, in
return inverse; return inverse;
} }
static ir_mode *get_spill_mode_mode(const ir_mode *mode)
{
if(mode_is_float(mode))
return mode_D;
return mode_Iu;
}
/** /**
* Get the mode that should be used for spilling value node * Get the mode that should be used for spilling value node
*/ */
static ir_mode *get_spill_mode(ia32_code_gen_t *cg, const ir_node *node) static ir_mode *get_spill_mode(const ir_node *node)
{ {
ir_mode *mode = get_irn_mode(node); ir_mode *mode = get_irn_mode(node);
if (mode_is_float(mode)) { return get_spill_mode_mode(mode);
#if 0
// super exact spilling...
if (USE_SSE2(cg))
return mode_D;
else
return mode_E;
#else
return mode_D;
#endif
}
else
return mode_Is;
assert(0);
return mode;
} }
/** /**
...@@ -803,11 +804,9 @@ static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spil ...@@ -803,11 +804,9 @@ static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spil
* @return Non-Zero if operand can be loaded * @return Non-Zero if operand can be loaded
*/ */
static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) { static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
const ia32_irn_ops_t *ops = self;
ia32_code_gen_t *cg = ops->cg;
ir_node *op = get_irn_n(irn, i); ir_node *op = get_irn_n(irn, i);
const ir_mode *mode = get_irn_mode(op); const ir_mode *mode = get_irn_mode(op);
const ir_mode *spillmode = get_spill_mode(cg, op); const ir_mode *spillmode = get_spill_mode(op);
if (! is_ia32_irn(irn) || /* must be an ia32 irn */ if (! is_ia32_irn(irn) || /* must be an ia32 irn */
get_irn_arity(irn) != 5 || /* must be a binary operation */ get_irn_arity(irn) != 5 || /* must be a binary operation */
...@@ -1032,7 +1031,7 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) { ...@@ -1032,7 +1031,7 @@ static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
ir_node *block = get_nodes_block(node); ir_node *block = get_nodes_block(node);
ir_entity *ent = be_get_frame_entity(node); ir_entity *ent = be_get_frame_entity(node);
ir_mode *mode = get_irn_mode(node); ir_mode *mode = get_irn_mode(node);
ir_mode *spillmode = get_spill_mode(cg, node); ir_mode *spillmode = get_spill_mode(node);
ir_node *noreg = ia32_new_NoReg_gp(cg); ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_node *sched_point = NULL; ir_node *sched_point = NULL;
ir_node *ptr = get_irg_frame(irg); ir_node *ptr = get_irg_frame(irg);
...@@ -1089,7 +1088,7 @@ static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) { ...@@ -1089,7 +1088,7 @@ static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
ir_node *block = get_nodes_block(node); ir_node *block = get_nodes_block(node);
ir_entity *ent = be_get_frame_entity(node); ir_entity *ent = be_get_frame_entity(node);
const ir_node *spillval = get_irn_n(node, be_pos_Spill_val); const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
ir_mode *mode = get_spill_mode(cg, spillval); ir_mode *mode = get_spill_mode(spillval);
ir_node *noreg = ia32_new_NoReg_gp(cg); ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_node *nomem = new_rd_NoMem(irg); ir_node *nomem = new_rd_NoMem(irg);
ir_node *ptr = get_irg_frame(irg); ir_node *ptr = get_irg_frame(irg);
...@@ -1302,12 +1301,12 @@ static void ia32_collect_frame_entity_nodes(ir_node *node, void *data) ...@@ -1302,12 +1301,12 @@ static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
be_fec_env_t *env = data; be_fec_env_t *env = data;
if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) { if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
const ir_mode *mode = get_irn_mode(node); const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
int align = get_mode_size_bytes(mode); int align = get_mode_size_bytes(mode);
be_node_needs_frame_entity(env, node, mode, align); be_node_needs_frame_entity(env, node, mode, align);
} else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
&& is_ia32_use_frame(node)) { && is_ia32_use_frame(node)) {
if (is_ia32_Load(node)) { if (is_ia32_got_reload(node) || is_ia32_Load(node)) {
const ir_mode *mode = get_ia32_ls_mode(node); const ir_mode *mode = get_ia32_ls_mode(node);
int align = get_mode_size_bytes(mode); int align = get_mode_size_bytes(mode);
be_node_needs_frame_entity(env, node, mode, align); be_node_needs_frame_entity(env, node, mode, align);
......
...@@ -375,6 +375,13 @@ void ia32_emit_mode_suffix(ia32_emit_env_t *env, const ir_mode *mode) ...@@ -375,6 +375,13 @@ void ia32_emit_mode_suffix(ia32_emit_env_t *env, const ir_mode *mode)
ia32_emit_char(env, get_mode_suffix(mode)); ia32_emit_char(env, get_mode_suffix(mode));
} }
void ia32_emit_x87_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
{
ir_mode *mode = get_ia32_ls_mode(node);
if(mode != NULL)
ia32_emit_mode_suffix(env, mode);
}
void ia32_emit_extend_suffix(ia32_emit_env_t *env, const ir_mode *mode) void ia32_emit_extend_suffix(ia32_emit_env_t *env, const ir_mode *mode)
{ {
if(get_mode_size_bits(mode) == 32) if(get_mode_size_bits(mode) == 32)
...@@ -930,7 +937,7 @@ static void emit_ia32_x87CondJmp(ia32_emit_env_t *env, const ir_node *node) { ...@@ -930,7 +937,7 @@ static void emit_ia32_x87CondJmp(ia32_emit_env_t *env, const ir_node *node) {
ia32_emit_cstring(env, "\tsahf"); ia32_emit_cstring(env, "\tsahf");
ia32_emit_finish_line(env, node); ia32_emit_finish_line(env, node);
finish_CondJmp(env, node, mode_D, pnc); finish_CondJmp(env, node, mode_E, pnc);
} }
static void CMov_emitter(ia32_emit_env_t *env, const ir_node *node) { static void CMov_emitter(ia32_emit_env_t *env, const ir_node *node) {
......
...@@ -49,6 +49,7 @@ void ia32_emit_dest_register(ia32_emit_env_t *env, const ir_node *node, int pos) ...@@ -49,6 +49,7 @@ void ia32_emit_dest_register(ia32_emit_env_t *env, const ir_node *node, int pos)
void ia32_emit_x87_name(ia32_emit_env_t *env, const ir_node *node, int pos); void ia32_emit_x87_name(ia32_emit_env_t *env, const ir_node *node, int pos);
void ia32_emit_immediate(ia32_emit_env_t *env, const ir_node *node); void ia32_emit_immediate(ia32_emit_env_t *env, const ir_node *node);
void ia32_emit_mode_suffix(ia32_emit_env_t *env, const ir_mode *mode); void ia32_emit_mode_suffix(ia32_emit_env_t *env, const ir_mode *mode);
void ia32_emit_x87_mode_suffix(ia32_emit_env_t *env, const ir_node *node);
void ia32_emit_extend_suffix(ia32_emit_env_t *env, const ir_mode *mode); void ia32_emit_extend_suffix(ia32_emit_env_t *env, const ir_mode *mode);
void ia32_emit_binop(ia32_emit_env_t *env, const ir_node *node); void ia32_emit_binop(ia32_emit_env_t *env, const ir_node *node);
void ia32_emit_unop(ia32_emit_env_t *env, const ir_node *node); void ia32_emit_unop(ia32_emit_env_t *env, const ir_node *node);
......
...@@ -330,7 +330,7 @@ insert_copy: ...@@ -330,7 +330,7 @@ insert_copy:
set_irn_n(irn, idx1, get_irn_n(irn, idx2)); set_irn_n(irn, idx1, get_irn_n(irn, idx2));
set_irn_n(irn, idx2, tmp); set_irn_n(irn, idx2, tmp);
set_ia32_pncode(irn, get_negated_pnc(pnc, mode_D)); set_ia32_pncode(irn, get_negated_pnc(pnc, mode_E));
} }
} }
......
...@@ -376,7 +376,7 @@ static int DivMod_mapper(ir_node *call, void *ctx, ia32_intrinsic_divmod_t dmtp) ...@@ -376,7 +376,7 @@ static int DivMod_mapper(ir_node *call, void *ctx, ia32_intrinsic_divmod_t dmtp)
set_ia32_use_frame(fa); set_ia32_use_frame(fa);
set_ia32_ls_mode(fa, mode_D); set_ia32_ls_mode(fa, mode_D);
fa_mem = new_r_Proj(irg, block, fa, mode_M, pn_ia32_l_vfild_M); fa_mem = new_r_Proj(irg, block, fa, mode_M, pn_ia32_l_vfild_M);
fa = new_r_Proj(irg, block, fa, mode_D, pn_ia32_l_vfild_res); fa = new_r_Proj(irg, block, fa, mode_E, pn_ia32_l_vfild_res);
/* store second arg */ /* store second arg */
store_l = new_rd_ia32_l_Store(dbg, irg, block, frame, b_l, get_irg_no_mem(irg)); store_l = new_rd_ia32_l_Store(dbg, irg, block, frame, b_l, get_irg_no_mem(irg));
...@@ -400,7 +400,7 @@ static int DivMod_mapper(ir_node *call, void *ctx, ia32_intrinsic_divmod_t dmtp) ...@@ -400,7 +400,7 @@ static int DivMod_mapper(ir_node *call, void *ctx, ia32_intrinsic_divmod_t dmtp)
set_ia32_use_frame(fb); set_ia32_use_frame(fb);
set_ia32_ls_mode(fb, mode_D); set_ia32_ls_mode(fb, mode_D);
fb_mem = new_r_Proj(irg, block, fb, mode_M, pn_ia32_l_vfild_M); fb_mem = new_r_Proj(irg, block, fb, mode_M, pn_ia32_l_vfild_M);
fb = new_r_Proj(irg, block, fb, mode_D, pn_ia32_l_vfild_res); fb = new_r_Proj(irg, block, fb, mode_E, pn_ia32_l_vfild_res);
op_mem[0] = fa_mem; op_mem[0] = fa_mem;
op_mem[1] = fb_mem; op_mem[1] = fb_mem;
...@@ -411,10 +411,10 @@ static int DivMod_mapper(ir_node *call, void *ctx, ia32_intrinsic_divmod_t dmtp) ...@@ -411,10 +411,10 @@ static int DivMod_mapper(ir_node *call, void *ctx, ia32_intrinsic_divmod_t dmtp)
switch (dmtp) { switch (dmtp) {
case IA32_INTRINSIC_DIV: case IA32_INTRINSIC_DIV:
fres = new_rd_ia32_l_vfdiv(dbg, irg, block, fa, fb); fres = new_rd_ia32_l_vfdiv(dbg, irg, block, fa, fb);
fres = new_rd_Proj(dbg, irg, block, fres, mode_D, pn_ia32_l_vfdiv_res); fres = new_rd_Proj(dbg, irg, block, fres, mode_E, pn_ia32_l_vfdiv_res);
break; break;
case IA32_INTRINSIC_MOD: case IA32_INTRINSIC_MOD:
fres = new_rd_ia32_l_vfprem(dbg, irg, block, fa, fb, mode_D); fres = new_rd_ia32_l_vfprem(dbg, irg, block, fa, fb, mode_E);
break; break;
default: default:
assert(0); assert(0);
......
...@@ -289,7 +289,7 @@ static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) { ...@@ -289,7 +289,7 @@ static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
for( ; i >= 0; --i) { for( ; i >= 0; --i) {
const arch_register_t *spreg; const arch_register_t *spreg;
ir_node *push; ir_node *push;
ir_node *val, *mem; ir_node *val, *mem, *mem_proj;
ir_node *store = stores[i]; ir_node *store = stores[i];
ir_node *noreg = ia32_new_NoReg_gp(cg); ir_node *noreg = ia32_new_NoReg_gp(cg);
...@@ -313,14 +313,14 @@ static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) { ...@@ -313,14 +313,14 @@ static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
arch_set_irn_register(cg->arch_env, curr_sp, spreg); arch_set_irn_register(cg->arch_env, curr_sp, spreg);
sched_add_before(irn, curr_sp); sched_add_before(irn, curr_sp);
// rewire users // create memory proj
edges_reroute(store, push, irg); mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
sched_add_before(irn, mem_proj);
// use the memproj now
exchange(store, mem_proj);
// we can remove the store now // we can remove the store now
set_irn_n(store, 0, new_Bad());
set_irn_n(store, 1, new_Bad());
set_irn_n(store, 2, new_Bad());
set_irn_n(store, 3, new_Bad());
sched_remove(store); sched_remove(store);
offset -= 4; offset -= 4;
......
...@@ -113,7 +113,7 @@ $arch = "ia32"; ...@@ -113,7 +113,7 @@ $arch = "ia32";
{ "name" => "edi", "type" => 2 }, { "name" => "edi", "type" => 2 },
{ "name" => "ebp", "type" => 2 }, { "name" => "ebp", "type" => 2 },
{ "name" => "esp", "type" => 4 }, { "name" => "esp", "type" => 4 },
{ "name" => "gp_NOREG", "type" => 4 | 16 }, # we need a dummy register for NoReg nodes { "name" => "gp_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
{ "name" => "gp_UKNWN", "type" => 4 | 8 | 16}, # we need a dummy register for Unknown nodes { "name" => "gp_UKNWN", "type" => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
{ "mode" => "mode_Iu" } { "mode" => "mode_Iu" }
], ],
...@@ -126,9 +126,9 @@ $arch = "ia32"; ...@@ -126,9 +126,9 @@ $arch = "ia32";
{ "name" => "xmm5", "type" => 1 }, { "name" => "xmm5", "type" => 1 },
{ "name" => "xmm6", "type" => 1 }, { "name" => "xmm6", "type" => 1 },
{ "name" => "xmm7", "type" => 1 }, { "name" => "xmm7", "type" => 1 },
{ "name" => "xmm_NOREG", "type" => 4 | 16 }, # we need a dummy register for NoReg nodes { "name" => "xmm_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
{ "name" => "xmm_UKNWN", "type" => 4 | 8 | 16}, # we need a dummy register for Unknown nodes { "name" => "xmm_UKNWN", "type" => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
{ "mode" => "mode_D" } { "mode" => "mode_E" }
], ],
"vfp" => [ "vfp" => [
{ "name" => "vf0", "type" => 1 | 16 }, { "name" => "vf0", "type" => 1 | 16 },
...@@ -139,9 +139,9 @@ $arch = "ia32"; ...@@ -139,9 +139,9 @@ $arch = "ia32";
{ "name" => "vf5", "type" => 1 | 16 }, { "name" => "vf5", "type" => 1 | 16 },
{ "name" => "vf6", "type" => 1 | 16 }, { "name" => "vf6", "type" => 1 | 16 },
{ "name" => "vf7", "type" => 1 | 16 }, { "name" => "vf7", "type" => 1 | 16 },
{ "name" => "vfp_NOREG", "type" => 4 | 16 }, # we need a dummy register for NoReg nodes { "name" => "vfp_NOREG", "type" => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
{ "name" => "vfp_UKNWN", "type" => 4 | 8 | 16}, # we need a dummy register for Unknown nodes { "name" => "vfp_UKNWN", "type" => 4 | 8 | 16}, # we need a dummy register for Unknown nodes
{ "mode" => "mode_D" } { "mode" => "mode_E" }
], ],
"st" => [ "st" => [
{ "name" => "st0", "type" => 1 }, { "name" => "st0", "type" => 1 },
...@@ -199,6 +199,7 @@ $arch = "ia32"; ...@@ -199,6 +199,7 @@ $arch = "ia32";
"ME" => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n "ME" => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
${arch}_emit_mode_suffix(env, get_ia32_ls_mode(node));", ${arch}_emit_mode_suffix(env, get_ia32_ls_mode(node));",
"M" => "${arch}_emit_mode_suffix(env, get_ia32_ls_mode(node));", "M" => "${arch}_emit_mode_suffix(env, get_ia32_ls_mode(node));",
"XM" => "${arch}_emit_x87_mode_suffix(env, node);",
"AM" => "${arch}_emit_am(env, node);", "AM" => "${arch}_emit_am(env, node);",
"unop" => "${arch}_emit_unop(env, node);", "unop" => "${arch}_emit_unop(env, node);",
"binop" => "${arch}_emit_binop(env, node);", "binop" => "${arch}_emit_binop(env, node);",
...@@ -717,7 +718,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { ...@@ -717,7 +718,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
"reg_req" => { "out" => [ "vfp_UKNWN" ] }, "reg_req" => { "out" => [ "vfp_UKNWN" ] },
"units" => [], "units" => [],
"emit" => "", "emit" => "",
"mode" => "mode_D" "mode" => "mode_E"
}, },
"Unknown_XMM" => { "Unknown_XMM" => {
...@@ -727,7 +728,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { ...@@ -727,7 +728,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
"reg_req" => { "out" => [ "xmm_UKNWN" ] }, "reg_req" => { "out" => [ "xmm_UKNWN" ] },
"units" => [], "units" => [],
"emit" => "", "emit" => "",
"mode" => "mode_D" "mode" => "mode_E"
}, },
"NoReg_GP" => { "NoReg_GP" => {
...@@ -747,7 +748,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { ...@@ -747,7 +748,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
"reg_req" => { "out" => [ "vfp_NOREG" ] }, "reg_req" => { "out" => [ "vfp_NOREG" ] },
"units" => [], "units" => [],
"emit" => "", "emit" => "",
"mode" => "mode_D" "mode" => "mode_E"
}, },
"NoReg_XMM" => { "NoReg_XMM" => {
...@@ -757,7 +758,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { ...@@ -757,7 +758,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
"reg_req" => { "out" => [ "xmm_NOREG" ] }, "reg_req" => { "out" => [ "xmm_NOREG" ] },
"units" => [], "units" => [],
"emit" => "", "emit" => "",
"mode" => "mode_D" "mode" => "mode_E"
}, },
"ChangeCW" => { "ChangeCW" => {
...@@ -944,7 +945,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { ...@@ -944,7 +945,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
"emit" => '. adds%M %binop', "emit" => '. adds%M %binop',
"latency" => 4, "latency" => 4,
"units" => [ "SSE" ], "units" => [ "SSE" ],
"mode" => "mode_D", "mode" => "mode_E",
}, },
"xMul" => { "xMul" => {
...@@ -954,7 +955,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { ...@@ -954,7 +955,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
"emit" => '. muls%M %binop', "emit" => '. muls%M %binop',
"latency" => 4, "latency" => 4,
"units" => [ "SSE" ], "units" => [ "SSE" ],
"mode" => "mode_D", "mode" => "mode_E",
}, },
"xMax" => { "xMax" => {
...@@ -964,7 +965,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { ...@@ -964,7 +965,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
"emit" => '. maxs%M %binop', "emit" => '. maxs%M %binop',
"latency" => 2, "latency" => 2,
"units" => [ "SSE" ], "units" => [ "SSE" ],
"mode" => "mode_D", "mode" => "mode_E",
}, },
"xMin" => { "xMin" => {
...@@ -974,7 +975,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { ...@@ -974,7 +975,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
"emit" => '. mins%M %binop', "emit" => '. mins%M %binop',
"latency" => 2, "latency" => 2,
"units" => [ "SSE" ], "units" => [ "SSE" ],
"mode" => "mode_D", "mode" => "mode_E",
}, },
"xAnd" => { "xAnd" => {
...@@ -984,7 +985,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { ...@@ -984,7 +985,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
"emit" => '. andp%M %binop', "emit" => '. andp%M %binop',
"latency" => 3, "latency" => 3,
"units" => [ "SSE" ], "units" => [ "SSE" ],
"mode" => "mode_D", "mode" => "mode_E",
}, },
"xOr" => { "xOr" => {
...@@ -993,7 +994,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { ...@@ -993,7 +994,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] }, "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3" ] },
"emit" => '. orp%M %binop', "emit" => '. orp%M %binop',
"units" => [ "SSE" ], "units" => [ "SSE" ],
"mode" => "mode_D", "mode" => "mode_E",
}, },
"xXor" => { "xXor" => {
...@@ -1003,7 +1004,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { ...@@ -1003,7 +1004,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
"emit" => '. xorp%M %binop', "emit" => '. xorp%M %binop',
"latency" => 3, "latency" => 3,
"units" => [ "SSE" ], "units" => [ "SSE" ],
"mode" => "mode_D", "mode" => "mode_E",
}, },
# not commutative operations # not commutative operations
...@@ -1015,7 +1016,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { ...@@ -1015,7 +1016,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
"emit" => '. andnp%M %binop', "emit" => '. andnp%M %binop',
"latency" => 3, "latency" => 3,
"units" => [ "SSE" ], "units" => [ "SSE" ],
"mode" => "mode_D", "mode" => "mode_E",
}, },
"xSub" => { "xSub" => {
...@@ -1025,7 +1026,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { ...@@ -1025,7 +1026,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
"emit" => '. subs%M %binop', "emit" => '. subs%M %binop',
"latency" => 4, "latency" => 4,
"units" => [ "SSE" ], "units" => [ "SSE" ],
"mode" => "mode_D", "mode" => "mode_E",
}, },
"xDiv" => { "xDiv" => {
...@@ -1046,7 +1047,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { ...@@ -1046,7 +1047,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
"reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] }, "reg_req" => { "in" => [ "gp", "gp", "xmm", "xmm", "none" ], "out" => [ "in_r3 !in_r4" ] },
"latency" => 3, "latency" => 3,
"units" => [ "SSE" ], "units" => [ "SSE" ],
"mode" => "mode_D", "mode" => "mode_E",
}, },
"xCondJmp" => { "xCondJmp" => {
...@@ -1066,7 +1067,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { ...@@ -1066,7 +1067,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
"emit" => '. movs%M %D1, $%C', "emit" => '. movs%M %D1, $%C',
"latency" => 2, "latency" => 2,
"units" => [ "SSE" ], "units" => [ "SSE" ],
"mode" => "mode_D", "mode" => "mode_E",
}, },
# Load / Store # Load / Store
...@@ -1183,7 +1184,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { ...@@ -1183,7 +1184,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
"comment" => "construct Conv Int -> Floating Point", "comment" => "construct Conv Int -> Floating Point",
"latency" => 10, "latency" => 10,
"units" => [ "SSE" ], "units" => [ "SSE" ],
"mode" => "mode_D", "mode" => "mode_E",
}, },
"Conv_FP2I" => { "Conv_FP2I" => {
...@@ -1199,7 +1200,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { ...@@ -1199,7 +1200,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
"comment" => "construct Conv Floating Point -> Floating Point", "comment" => "construct Conv Floating Point -> Floating Point",
"latency" => 8, "latency" => 8,
"units" => [ "SSE" ], "units" => [ "SSE" ],
"mode" => "mode_D", "mode" => "mode_E",
}, },
"CmpCMov" => { "CmpCMov" => {
...@@ -1280,7 +1281,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) { ...@@ -1280,7 +1281,7 @@ if (get_ia32_immop_type(node) == ia32_ImmNone) {
"reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] }, "reg_req" => { "in" => [ "vfp", "vfp", "vfp", "vfp" ], "out" => [ "vfp" ] },
"latency" => 10, "latency" => 10,
"units" => [ "VFP" ], "units" => [ "VFP" ],
"mode" => "mode_D", "mode" => "mode_E",
}, },