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Zwinkau
libfirm
Commits
d02e1f6b
Commit
d02e1f6b
authored
Nov 14, 2010
by
Michael Beck
Browse files
Prefix global entities from the ia32 backend with ia32_ to prevent (future) collisitions.
[r28139]
parent
567bd376
Changes
10
Hide whitespace changes
Inline
Side-by-side
ir/be/ia32/bearch_ia32.c
View file @
d02e1f6b
...
...
@@ -97,7 +97,7 @@ transformer_t be_transformer = TRANSFORMER_DEFAULT;
DEBUG_ONLY
(
static
firm_dbg_module_t
*
dbg
=
NULL
;)
ir_mode
*
mode_fpcw
=
NULL
;
ir_mode
*
ia32_
mode_fpcw
=
NULL
;
/** The current omit-fp state */
static
unsigned
ia32_curr_fp_ommitted
=
0
;
...
...
@@ -851,7 +851,7 @@ static void ia32_prepare_graph(ir_graph *irg)
dump_ir_graph
(
irg
,
"place"
);
}
ir_node
*
turn_back_am
(
ir_node
*
node
)
ir_node
*
ia32_
turn_back_am
(
ir_node
*
node
)
{
dbg_info
*
dbgi
=
get_irn_dbg_info
(
node
);
ir_graph
*
irg
=
get_irn_irg
(
node
);
...
...
@@ -929,7 +929,7 @@ static ir_node *flags_remat(ir_node *node, ir_node *after)
type
=
get_ia32_op_type
(
node
);
switch
(
type
)
{
case
ia32_AddrModeS
:
turn_back_am
(
node
);
ia32_
turn_back_am
(
node
);
break
;
case
ia32_AddrModeD
:
...
...
@@ -1348,7 +1348,7 @@ static void ia32_finish(ir_graph *irg)
/* we might have to rewrite x87 virtual registers */
if
(
irg_data
->
do_x87_sim
)
{
x87_simulate_graph
(
irg
);
ia32_
x87_simulate_graph
(
irg
);
}
/* do peephole optimisations */
...
...
@@ -1531,8 +1531,8 @@ static arch_env_t *ia32_init(FILE *file_handle)
isa
=
XMALLOC
(
ia32_isa_t
);
memcpy
(
isa
,
&
ia32_isa_template
,
sizeof
(
*
isa
));
if
(
mode_fpcw
==
NULL
)
{
mode_fpcw
=
new_ir_mode
(
"Fpcw"
,
irms_int_number
,
16
,
0
,
irma_none
,
0
);
if
(
ia32_
mode_fpcw
==
NULL
)
{
ia32_
mode_fpcw
=
new_ir_mode
(
"Fpcw"
,
irms_int_number
,
16
,
0
,
irma_none
,
0
);
}
ia32_register_init
();
...
...
ir/be/ia32/bearch_ia32_t.h
View file @
d02e1f6b
...
...
@@ -101,7 +101,7 @@ extern transformer_t be_transformer;
#endif
/** The mode for the floating point control word. */
extern
ir_mode
*
mode_fpcw
;
extern
ir_mode
*
ia32_
mode_fpcw
;
static
inline
ia32_irg_data_t
*
ia32_get_irg_data
(
const
ir_graph
*
irg
)
{
...
...
@@ -124,7 +124,7 @@ ir_node *ia32_new_Fpu_truncate(ir_graph *irg);
* Split instruction with source AM into Load and separate instruction.
* @return result of the Load
*/
ir_node
*
turn_back_am
(
ir_node
*
node
);
ir_node
*
ia32_
turn_back_am
(
ir_node
*
node
);
/**
* Maps all intrinsic calls that the backend support
...
...
ir/be/ia32/ia32_common_transform.c
View file @
d02e1f6b
...
...
@@ -44,7 +44,7 @@
#include
"gen_ia32_new_nodes.h"
#include
"gen_ia32_regalloc_if.h"
ir_heights_t
*
heights
=
NULL
;
ir_heights_t
*
ia32_
heights
=
NULL
;
static
int
check_immediate_constraint
(
long
val
,
char
immediate_constraint_type
)
{
...
...
@@ -81,7 +81,7 @@ static ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
return
res
;
}
ir_entity
*
create_float_const_entity
(
ir_node
*
cnst
)
ir_entity
*
ia32_
create_float_const_entity
(
ir_node
*
cnst
)
{
ir_graph
*
irg
=
get_irn_irg
(
cnst
);
const
arch_env_t
*
arch_env
=
be_get_irg_arch_env
(
irg
);
...
...
@@ -130,7 +130,7 @@ ir_node *ia32_create_Immediate(ir_entity *symconst, int symconst_sign, long val)
ir_graph
*
irg
=
current_ir_graph
;
ir_node
*
start_block
=
get_irg_start_block
(
irg
);
ir_node
*
immediate
=
new_bd_ia32_Immediate
(
NULL
,
start_block
,
symconst
,
symconst_sign
,
no_pic_adjust
,
val
);
symconst_sign
,
ia32_
no_pic_adjust
,
val
);
arch_set_irn_register
(
immediate
,
&
ia32_registers
[
REG_GP_NOREG
]);
return
immediate
;
...
...
@@ -164,7 +164,7 @@ const arch_register_t *ia32_get_clobber_register(const char *clobber)
int
ia32_mode_needs_gp_reg
(
ir_mode
*
mode
)
{
if
(
mode
==
mode_fpcw
)
if
(
mode
==
ia32_
mode_fpcw
)
return
0
;
if
(
get_mode_size_bits
(
mode
)
>
32
)
return
0
;
...
...
@@ -425,7 +425,7 @@ static inline ir_node *get_new_node(ir_node *node)
#endif
}
ir_node
*
gen_ASM
(
ir_node
*
node
)
ir_node
*
ia32_
gen_ASM
(
ir_node
*
node
)
{
ir_node
*
block
=
get_nodes_block
(
node
);
ir_node
*
new_block
=
get_new_node
(
block
);
...
...
@@ -476,7 +476,7 @@ ir_node *gen_ASM(ir_node *node)
continue
;
}
req
=
parse_clobber
(
c
);
req
=
ia32_
parse_clobber
(
c
);
clobber_bits
[
req
->
cls
->
index
]
|=
*
req
->
limited
;
n_clobbers
++
;
...
...
@@ -516,7 +516,7 @@ ir_node *gen_ASM(ir_node *node)
const
arch_register_req_t
*
req
;
parse_asm_constraints
(
&
parsed_constraint
,
c
,
1
);
req
=
make_register_req
(
&
parsed_constraint
,
n_out_constraints
,
req
=
ia32_
make_register_req
(
&
parsed_constraint
,
n_out_constraints
,
out_reg_reqs
,
out_idx
);
out_reg_reqs
[
out_idx
]
=
req
;
...
...
@@ -555,13 +555,13 @@ ir_node *gen_ASM(ir_node *node)
}
}
req
=
make_register_req
(
&
parsed_constraint
,
n_out_constraints
,
req
=
ia32_
make_register_req
(
&
parsed_constraint
,
n_out_constraints
,
out_reg_reqs
,
i
);
in_reg_reqs
[
i
]
=
req
;
if
(
parsed_constraint
.
immediate_type
!=
'\0'
)
{
char
imm_type
=
parsed_constraint
.
immediate_type
;
input
=
try_create_Immediate
(
pred
,
imm_type
);
input
=
ia32_
try_create_Immediate
(
pred
,
imm_type
);
}
if
(
input
==
NULL
)
{
...
...
@@ -592,7 +592,7 @@ ir_node *gen_ASM(ir_node *node)
if
(
strcmp
(
c
,
"memory"
)
==
0
||
strcmp
(
c
,
"cc"
)
==
0
)
continue
;
req
=
parse_clobber
(
c
);
req
=
ia32_
parse_clobber
(
c
);
out_reg_reqs
[
out_idx
]
=
req
;
++
out_idx
;
}
...
...
@@ -746,7 +746,7 @@ ir_node *gen_ASM(ir_node *node)
return
new_node
;
}
ir_node
*
gen_CopyB
(
ir_node
*
node
)
ir_node
*
ia32_
gen_CopyB
(
ir_node
*
node
)
{
ir_node
*
block
=
get_new_node
(
get_nodes_block
(
node
));
ir_node
*
src
=
get_CopyB_src
(
node
);
...
...
@@ -783,7 +783,7 @@ ir_node *gen_CopyB(ir_node *node)
return
res
;
}
ir_node
*
gen_Proj_tls
(
ir_node
*
node
)
ir_node
*
ia32_
gen_Proj_tls
(
ir_node
*
node
)
{
ir_node
*
block
=
get_new_node
(
get_nodes_block
(
node
));
ir_node
*
res
=
NULL
;
...
...
@@ -793,7 +793,7 @@ ir_node *gen_Proj_tls(ir_node *node)
return
res
;
}
ir_node
*
gen_Unknown
(
ir_node
*
node
)
ir_node
*
ia32_
gen_Unknown
(
ir_node
*
node
)
{
ir_mode
*
mode
=
get_irn_mode
(
node
);
ir_graph
*
irg
=
current_ir_graph
;
...
...
@@ -817,7 +817,7 @@ ir_node *gen_Unknown(ir_node *node)
return
res
;
}
const
arch_register_req_t
*
make_register_req
(
const
constraint_t
*
constraint
,
const
arch_register_req_t
*
ia32_
make_register_req
(
const
constraint_t
*
constraint
,
int
n_outs
,
const
arch_register_req_t
**
out_reqs
,
int
pos
)
{
struct
obstack
*
obst
=
get_irg_obstack
(
current_ir_graph
);
...
...
@@ -871,7 +871,7 @@ const arch_register_req_t *make_register_req(const constraint_t *constraint,
return
req
;
}
const
arch_register_req_t
*
parse_clobber
(
const
char
*
clobber
)
const
arch_register_req_t
*
ia32_
parse_clobber
(
const
char
*
clobber
)
{
struct
obstack
*
obst
=
get_irg_obstack
(
current_ir_graph
);
const
arch_register_t
*
reg
=
ia32_get_clobber_register
(
clobber
);
...
...
@@ -897,7 +897,7 @@ const arch_register_req_t *parse_clobber(const char *clobber)
}
int
prevents_AM
(
ir_node
*
const
block
,
ir_node
*
const
am_candidate
,
int
ia32_
prevents_AM
(
ir_node
*
const
block
,
ir_node
*
const
am_candidate
,
ir_node
*
const
other
)
{
if
(
get_nodes_block
(
other
)
!=
block
)
...
...
@@ -916,7 +916,7 @@ int prevents_AM(ir_node *const block, ir_node *const am_candidate,
if
(
is_Proj
(
pred
)
&&
get_Proj_pred
(
pred
)
==
am_candidate
)
continue
;
if
(
!
heights_reachable_in_block
(
heights
,
pred
,
am_candidate
))
if
(
!
heights_reachable_in_block
(
ia32_
heights
,
pred
,
am_candidate
))
continue
;
return
1
;
...
...
@@ -928,14 +928,14 @@ int prevents_AM(ir_node *const block, ir_node *const am_candidate,
if
(
is_Proj
(
other
)
&&
get_Proj_pred
(
other
)
==
am_candidate
)
return
0
;
if
(
!
heights_reachable_in_block
(
heights
,
other
,
am_candidate
))
if
(
!
heights_reachable_in_block
(
ia32_
heights
,
other
,
am_candidate
))
return
0
;
return
1
;
}
}
ir_node
*
try_create_Immediate
(
ir_node
*
node
,
char
immediate_constraint_type
)
ir_node
*
ia32_
try_create_Immediate
(
ir_node
*
node
,
char
immediate_constraint_type
)
{
long
val
=
0
;
ir_entity
*
symconst_ent
=
NULL
;
...
...
ir/be/ia32/ia32_common_transform.h
View file @
d02e1f6b
...
...
@@ -43,8 +43,8 @@ struct constraint_t {
int
same_as
;
};
extern
ir_heights_t
*
heights
;
extern
int
no_pic_adjust
;
extern
ir_heights_t
*
ia32_
heights
;
extern
int
ia32_
no_pic_adjust
;
/**
* Get an atomic entity that is initialized with a tarval forming
...
...
@@ -52,7 +52,7 @@ extern int no_pic_adjust;
*
* @param cnst the node representing the constant
*/
ir_entity
*
create_float_const_entity
(
ir_node
*
cnst
);
ir_entity
*
ia32_
create_float_const_entity
(
ir_node
*
cnst
);
/**
* Creates an immediate.
...
...
@@ -77,38 +77,38 @@ int ia32_mode_needs_gp_reg(ir_mode *mode);
/**
* generates code for a ASM node
*/
ir_node
*
gen_ASM
(
ir_node
*
node
);
ir_node
*
ia32_
gen_ASM
(
ir_node
*
node
);
/**
* Transforms a CopyB node.
*
* @return The transformed node.
*/
ir_node
*
gen_CopyB
(
ir_node
*
node
);
ir_node
*
ia32_
gen_CopyB
(
ir_node
*
node
);
/**
* Transform the Thread Local Storage Proj.
*/
ir_node
*
gen_Proj_tls
(
ir_node
*
node
);
ir_node
*
ia32_
gen_Proj_tls
(
ir_node
*
node
);
/**
* This function just sets the register for the Unknown node
* as this is not done during register allocation because Unknown
* is an "ignore" node.
*/
ir_node
*
gen_Unknown
(
ir_node
*
node
);
ir_node
*
ia32_
gen_Unknown
(
ir_node
*
node
);
const
arch_register_req_t
*
make_register_req
(
const
constraint_t
*
constraint
,
const
arch_register_req_t
*
ia32_
make_register_req
(
const
constraint_t
*
constraint
,
int
n_outs
,
const
arch_register_req_t
**
out_reqs
,
int
pos
);
const
arch_register_req_t
*
parse_clobber
(
const
char
*
clobber
);
const
arch_register_req_t
*
ia32_
parse_clobber
(
const
char
*
clobber
);
/**
* Checks whether other node inputs depend on the am_candidate (via mem-proj).
*/
int
prevents_AM
(
ir_node
*
const
block
,
ir_node
*
const
am_candidate
,
int
ia32_
prevents_AM
(
ir_node
*
const
block
,
ir_node
*
const
am_candidate
,
ir_node
*
const
other
);
ir_node
*
try_create_Immediate
(
ir_node
*
node
,
char
immediate_constraint_type
);
ir_node
*
ia32_
try_create_Immediate
(
ir_node
*
node
,
char
immediate_constraint_type
);
#endif
ir/be/ia32/ia32_finish.c
View file @
d02e1f6b
...
...
@@ -426,7 +426,7 @@ static void fix_am_source(ir_node *irn)
out_reg
!=
arch_get_irn_register
(
get_irn_n
(
irn
,
n_ia32_index
)))
continue
;
load_res
=
turn_back_am
(
irn
);
load_res
=
ia32_
turn_back_am
(
irn
);
arch_set_irn_register
(
load_res
,
out_reg
);
DBG
((
dbg
,
LEVEL_3
,
...
...
ir/be/ia32/ia32_optimize.c
View file @
d02e1f6b
...
...
@@ -644,7 +644,7 @@ static void peephole_store_incsp(ir_node *store)
*/
static
inline
int
mode_needs_gp_reg
(
ir_mode
*
mode
)
{
if
(
mode
==
mode_fpcw
)
if
(
mode
==
ia32_
mode_fpcw
)
return
0
;
if
(
get_mode_size_bits
(
mode
)
>
32
)
return
0
;
...
...
@@ -1202,7 +1202,7 @@ static void peephole_ia32_Imul_split(ir_node *imul)
return
;
/* fine, we can rebuild it */
res
=
turn_back_am
(
imul
);
res
=
ia32_
turn_back_am
(
imul
);
arch_set_irn_register
(
res
,
reg
);
}
...
...
ir/be/ia32/ia32_spec.pl
View file @
d02e1f6b
...
...
@@ -74,7 +74,7 @@ $state = 32; # register represents a state
],
fp_cw
=>
[
# the floating point control word
{
name
=>
"
fpcw
",
type
=>
$ignore
|
$state
},
{
mode
=>
"
mode_fpcw
",
flags
=>
"
manual_ra|state
"
}
{
mode
=>
"
ia32_
mode_fpcw
",
flags
=>
"
manual_ra|state
"
}
],
flags
=>
[
{
name
=>
"
eflags
",
type
=>
0
},
...
...
@@ -209,7 +209,7 @@ $custom_init_attr_func = \&ia32_custom_init_attr;
$mode_xmm
=
"
mode_E
";
$mode_gp
=
"
mode_Iu
";
$mode_flags
=
"
mode_Iu
";
$mode_fpcw
=
"
mode_fpcw
";
$mode_fpcw
=
"
ia32_
mode_fpcw
";
$status_flags
=
[
"
CF
",
"
PF
",
"
AF
",
"
ZF
",
"
SF
",
"
OF
"
];
$status_flags_wo_cf
=
[
"
PF
",
"
AF
",
"
ZF
",
"
SF
",
"
OF
"
];
$fpcw_flags
=
[
"
FP_IM
",
"
FP_DM
",
"
FP_ZM
",
"
FP_OM
",
"
FP_UM
",
"
FP_PM
",
...
...
ir/be/ia32/ia32_transform.c
View file @
d02e1f6b
...
...
@@ -92,7 +92,7 @@
DEBUG_ONLY
(
static
firm_dbg_module_t
*
dbg
=
NULL
;)
static
ir_node
*
initial_fpcw
=
NULL
;
int
no_pic_adjust
;
int
ia32_
no_pic_adjust
;
typedef
ir_node
*
construct_binop_func
(
dbg_info
*
db
,
ir_node
*
block
,
ir_node
*
base
,
ir_node
*
index
,
ir_node
*
mem
,
ir_node
*
op1
,
...
...
@@ -285,7 +285,7 @@ static ir_node *gen_Const(ir_node *node)
}
}
#endif
/* CONSTRUCT_SSE_CONST */
floatent
=
create_float_const_entity
(
node
);
floatent
=
ia32_
create_float_const_entity
(
node
);
base
=
get_symconst_base
();
load
=
new_bd_ia32_xLoad
(
dbgi
,
block
,
base
,
noreg_GP
,
nomem
,
...
...
@@ -308,7 +308,7 @@ static ir_node *gen_Const(ir_node *node)
ir_mode
*
ls_mode
;
ir_node
*
base
;
floatent
=
create_float_const_entity
(
node
);
floatent
=
ia32_
create_float_const_entity
(
node
);
/* create_float_const_ent is smart and sometimes creates
smaller entities */
ls_mode
=
get_type_mode
(
get_entity_type
(
floatent
));
...
...
@@ -591,10 +591,10 @@ static int ia32_use_source_address_mode(ir_node *block, ir_node *node,
return
0
;
/* don't do AM if other node inputs depend on the load (via mem-proj) */
if
(
other
!=
NULL
&&
prevents_AM
(
block
,
load
,
other
))
if
(
other
!=
NULL
&&
ia32_
prevents_AM
(
block
,
load
,
other
))
return
0
;
if
(
other2
!=
NULL
&&
prevents_AM
(
block
,
load
,
other2
))
if
(
other2
!=
NULL
&&
ia32_
prevents_AM
(
block
,
load
,
other2
))
return
0
;
return
1
;
...
...
@@ -636,7 +636,7 @@ static void build_address(ia32_address_mode_t *am, ir_node *node,
/* floating point immediates */
if
(
is_Const
(
node
))
{
ir_entity
*
entity
=
create_float_const_entity
(
node
);
ir_entity
*
entity
=
ia32_
create_float_const_entity
(
node
);
addr
->
base
=
get_symconst_base
();
addr
->
index
=
noreg_GP
;
addr
->
mem
=
nomem
;
...
...
@@ -842,7 +842,7 @@ static void match_arguments(ia32_address_mode_t *am, ir_node *block,
* op2 input */
new_op2
=
NULL
;
if
(
!
(
flags
&
match_try_am
)
&&
use_immediate
)
{
new_op2
=
try_create_Immediate
(
op2
,
0
);
new_op2
=
ia32_
try_create_Immediate
(
op2
,
0
);
}
if
(
new_op2
==
NULL
&&
...
...
@@ -2105,14 +2105,14 @@ static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
/* don't do AM if other node inputs depend on the load (via mem-proj) */
if
(
other
!=
NULL
&&
get_nodes_block
(
other
)
==
block
&&
heights_reachable_in_block
(
heights
,
other
,
load
))
{
heights_reachable_in_block
(
ia32_
heights
,
other
,
load
))
{
return
0
;
}
if
(
prevents_AM
(
block
,
load
,
mem
))
if
(
ia32_
prevents_AM
(
block
,
load
,
mem
))
return
0
;
/* Store should be attached to the load via mem */
assert
(
heights_reachable_in_block
(
heights
,
mem
,
load
));
assert
(
heights_reachable_in_block
(
ia32_
heights
,
mem
,
load
));
return
1
;
}
...
...
@@ -3874,7 +3874,7 @@ static ir_node *gen_Conv(ir_node *node)
static
ir_node
*
create_immediate_or_transform
(
ir_node
*
node
,
char
immediate_constraint_type
)
{
ir_node
*
new_node
=
try_create_Immediate
(
node
,
immediate_constraint_type
);
ir_node
*
new_node
=
ia32_
try_create_Immediate
(
node
,
immediate_constraint_type
);
if
(
new_node
==
NULL
)
{
new_node
=
be_transform_node
(
node
);
}
...
...
@@ -4746,13 +4746,13 @@ static ir_node *gen_be_Call(ir_node *node)
assert
(
be_Call_get_entity
(
node
)
==
NULL
);
/* special case for PIC trampoline calls */
old_no_pic_adjust
=
no_pic_adjust
;
no_pic_adjust
=
be_get_irg_options
(
current_ir_graph
)
->
pic
;
old_no_pic_adjust
=
ia32_
no_pic_adjust
;
ia32_
no_pic_adjust
=
be_get_irg_options
(
current_ir_graph
)
->
pic
;
match_arguments
(
&
am
,
src_block
,
NULL
,
src_ptr
,
src_mem
,
match_am
|
match_immediate
);
no_pic_adjust
=
old_no_pic_adjust
;
ia32_
no_pic_adjust
=
old_no_pic_adjust
;
i
=
get_irn_arity
(
node
)
-
1
;
fpcw
=
be_transform_node
(
get_irn_n
(
node
,
i
--
));
...
...
@@ -5656,7 +5656,7 @@ static ir_node *gen_Proj(ir_node *node)
}
case
pn_Start_P_tls
:
return
gen_Proj_tls
(
node
);
return
ia32_
gen_Proj_tls
(
node
);
}
break
;
...
...
@@ -5691,7 +5691,7 @@ static void register_transformers(void)
be_set_transform_function
(
op_Add
,
gen_Add
);
be_set_transform_function
(
op_And
,
gen_And
);
be_set_transform_function
(
op_ASM
,
gen_ASM
);
be_set_transform_function
(
op_ASM
,
ia32_
gen_ASM
);
be_set_transform_function
(
op_be_AddSP
,
gen_be_AddSP
);
be_set_transform_function
(
op_be_Call
,
gen_be_Call
);
be_set_transform_function
(
op_be_Copy
,
gen_be_Copy
);
...
...
@@ -5705,7 +5705,7 @@ static void register_transformers(void)
be_set_transform_function
(
op_Cond
,
gen_Cond
);
be_set_transform_function
(
op_Const
,
gen_Const
);
be_set_transform_function
(
op_Conv
,
gen_Conv
);
be_set_transform_function
(
op_CopyB
,
gen_CopyB
);
be_set_transform_function
(
op_CopyB
,
ia32_
gen_CopyB
);
be_set_transform_function
(
op_Div
,
gen_Div
);
be_set_transform_function
(
op_DivMod
,
gen_DivMod
);
be_set_transform_function
(
op_Eor
,
gen_Eor
);
...
...
@@ -5750,7 +5750,7 @@ static void register_transformers(void)
be_set_transform_function
(
op_Store
,
gen_Store
);
be_set_transform_function
(
op_Sub
,
gen_Sub
);
be_set_transform_function
(
op_SymConst
,
gen_SymConst
);
be_set_transform_function
(
op_Unknown
,
gen_Unknown
);
be_set_transform_function
(
op_Unknown
,
ia32_
gen_Unknown
);
}
/**
...
...
@@ -5871,11 +5871,11 @@ void ia32_transform_graph(ir_graph *irg)
int
cse_last
;
register_transformers
();
initial_fpcw
=
NULL
;
no_pic_adjust
=
0
;
initial_fpcw
=
NULL
;
ia32_
no_pic_adjust
=
0
;
be_timer_push
(
T_HEIGHTS
);
heights
=
heights_new
(
irg
);
ia32_
heights
=
heights_new
(
irg
);
be_timer_pop
(
T_HEIGHTS
);
ia32_calculate_non_address_mode_nodes
(
irg
);
...
...
@@ -5896,8 +5896,8 @@ void ia32_transform_graph(ir_graph *irg)
set_opt_cse
(
cse_last
);
ia32_free_non_address_mode_nodes
();
heights_free
(
heights
);
heights
=
NULL
;
heights_free
(
ia32_
heights
);
ia32_
heights
=
NULL
;
}
void
ia32_init_transform
(
void
)
...
...
ir/be/ia32/ia32_x87.c
View file @
d02e1f6b
...
...
@@ -2268,7 +2268,7 @@ static void update_liveness_walker(ir_node *block, void *data)
* Replaces all virtual floating point instructions and registers
* by real ones.
*/
void
x87_simulate_graph
(
ir_graph
*
irg
)
void
ia32_
x87_simulate_graph
(
ir_graph
*
irg
)
{
/* TODO improve code quality (less executed fxch) by using execfreqs */
...
...
@@ -2310,7 +2310,7 @@ void x87_simulate_graph(ir_graph *irg)
/* kill it */
del_waitq
(
sim
.
worklist
);
x87_destroy_simulator
(
&
sim
);
}
/* x87_simulate_graph */
}
/*
ia32_
x87_simulate_graph */
/* Initializes the x87 simulator. */
void
ia32_init_x87
(
void
)
...
...
ir/be/ia32/ia32_x87.h
View file @
d02e1f6b
...
...
@@ -39,7 +39,7 @@
*
* Registers must be allocated.
*/
void
x87_simulate_graph
(
ir_graph
*
irg
);
void
ia32_
x87_simulate_graph
(
ir_graph
*
irg
);
/**
* Initializes the x87 simulator.
...
...
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