Commit d4bbab11 authored by Christoph Mallon's avatar Christoph Mallon
Browse files

Remove the unused parameter const arch_env_t *env from arch_get_irn_register().

[r22697]
parent a910bf06
......@@ -48,8 +48,6 @@
#define SNPRINTF_BUF_LEN 128
static const arch_env_t *arch_env;
/**
* Returns the register at in position pos.
*/
......@@ -64,7 +62,7 @@ static const arch_register_t *get_in_reg(const ir_node *node, int pos)
in register we need. */
op = get_irn_n(node, pos);
reg = arch_get_irn_register(arch_env, op);
reg = arch_get_irn_register(op);
assert(reg && "no in register found");
return reg;
......@@ -84,7 +82,7 @@ static const arch_register_t *get_out_reg(const ir_node *node, int pos)
/* Proj with the corresponding projnum for the register */
if (get_irn_mode(node) != mode_T) {
reg = arch_get_irn_register(arch_env, node);
reg = arch_get_irn_register(node);
} else if (is_TEMPLATE_irn(node)) {
reg = get_TEMPLATE_out_reg(node, pos);
} else {
......@@ -94,7 +92,7 @@ static const arch_register_t *get_out_reg(const ir_node *node, int pos)
proj = get_edge_src_irn(edge);
assert(is_Proj(proj) && "non-Proj from mode_T node");
if (get_Proj_proj(proj) == pos) {
reg = arch_get_irn_register(arch_env, proj);
reg = arch_get_irn_register(proj);
break;
}
}
......@@ -273,9 +271,9 @@ void TEMPLATE_gen_labels(ir_node *block, void *env) {
/**
* Main driver
*/
void TEMPLATE_gen_routine(const TEMPLATE_code_gen_t *cg, ir_graph *irg) {
arch_env = cg->arch_env;
void TEMPLATE_gen_routine(const TEMPLATE_code_gen_t *cg, ir_graph *irg)
{
(void)cg;
/* register all emitter functions */
TEMPLATE_register_emitters();
......
......@@ -67,7 +67,6 @@
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
static const arch_env_t *arch_env = NULL;
static const arm_code_gen_t *cg;
static const arm_isa_t *isa;
static set *sym_or_tv;
......@@ -85,7 +84,7 @@ static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
in register we need. */
op = get_irn_n(irn, pos);
reg = arch_get_irn_register(arch_env, op);
reg = arch_get_irn_register(op);
assert(reg && "no in register found");
......@@ -120,7 +119,7 @@ static const arch_register_t *get_out_reg(const ir_node *node, int pos)
/* Proj with the corresponding projnum for the register */
if (get_irn_mode(node) != mode_T) {
reg = arch_get_irn_register(arch_env, node);
reg = arch_get_irn_register(node);
} else if (is_arm_irn(node)) {
reg = get_arm_out_reg(node, pos);
} else {
......@@ -130,7 +129,7 @@ static const arch_register_t *get_out_reg(const ir_node *node, int pos)
proj = get_edge_src_irn(edge);
assert(is_Proj(proj) && "non-Proj from mode_T node");
if (get_Proj_proj(proj) == pos) {
reg = arch_get_irn_register(arch_env, proj);
reg = arch_get_irn_register(proj);
break;
}
}
......@@ -1204,7 +1203,6 @@ void arm_gen_routine(const arm_code_gen_t *arm_cg, ir_graph *irg) {
cg = arm_cg;
isa = (const arm_isa_t *)cg->arch_env;
arch_env = cg->arch_env;
sym_or_tv = new_set(cmp_sym_or_tv, 8);
arm_register_emitters();
......
......@@ -275,7 +275,7 @@ static void peephole_be_Reload(ir_node *node) {
ptr = gen_ptr_sub(node, frame, &v);
}
reg = arch_get_irn_register(arch_env, node);
reg = arch_get_irn_register(node);
mem = be_get_Reload_mem(node);
mode = get_irn_mode(node);
irg = current_ir_graph;
......
......@@ -774,7 +774,7 @@ static ir_node *adjust_call(be_abi_irg_t *env, ir_node *irn, ir_node *curr_sp)
for(i = 0; i < n_reg_results; ++i) {
ir_node *proj = res_projs[i];
const arch_register_t *reg = arch_get_irn_register(arch_env, proj);
const arch_register_t *reg = arch_get_irn_register(proj);
set_irn_link(proj, (void*) reg);
obstack_ptr_grow(obst, proj);
}
......
......@@ -220,11 +220,9 @@ const arch_register_class_t *arch_get_irn_reg_class(const ir_node *irn, int pos)
return req->cls;
}
extern const arch_register_t *
arch_get_irn_register(const arch_env_t *env, const ir_node *irn)
const arch_register_t *arch_get_irn_register(const ir_node *irn)
{
const arch_irn_ops_t *ops = get_irn_ops(irn);
(void)env; // TODO remove parameter
return ops->get_irn_reg(irn);
}
......
......@@ -203,12 +203,10 @@ const arch_register_class_t *arch_get_irn_reg_class(const ir_node *irn, int pos)
/**
* Get the register allocated at a certain output operand of a node.
* @param env The arch environment.
* @param irn The node.
* @return The register allocated for this operand
*/
extern const arch_register_t *
arch_get_irn_register(const arch_env_t *env, const ir_node *irn);
const arch_register_t *arch_get_irn_register(const ir_node *irn);
/**
* Set the register for a certain output operand.
......
......@@ -229,12 +229,11 @@ static be_insn_t *chordal_scan_insn(be_chordal_env_t *env, ir_node *irn)
static ir_node *prepare_constr_insn(be_chordal_env_t *env, ir_node *irn)
{
const be_irg_t *birg = env->birg;
const arch_env_t *aenv = birg->main_env->arch_env;
bitset_t *tmp = bitset_alloca(env->cls->n_regs);
bitset_t *def_constr = bitset_alloca(env->cls->n_regs);
ir_node *bl = get_nodes_block(irn);
be_lv_t *lv = env->birg->lv;
const be_irg_t *birg = env->birg;
be_lv_t *lv = birg->lv;
be_insn_t *insn;
int i, j;
......@@ -248,7 +247,7 @@ static ir_node *prepare_constr_insn(be_chordal_env_t *env, ir_node *irn)
if (arch_get_irn_reg_class(irn, i) != env->cls)
continue;
reg = arch_get_irn_register(aenv, op);
reg = arch_get_irn_register(op);
if (reg == NULL || !arch_register_type_is(reg, ignore))
continue;
......@@ -692,7 +691,7 @@ static ir_node *handle_constraints(be_chordal_alloc_env_t *alloc_env,
/* Put the colors of all Projs in a bitset. */
foreach_out_edge(perm, edge) {
ir_node *proj = get_edge_src_irn(edge);
const arch_register_t *reg = arch_get_irn_register(aenv, proj);
const arch_register_t *reg = arch_get_irn_register(proj);
if(reg != NULL)
bitset_set(bs, reg->index);
......@@ -701,7 +700,7 @@ static ir_node *handle_constraints(be_chordal_alloc_env_t *alloc_env,
/* Assign the not yet assigned Projs of the Perm a suitable color. */
foreach_out_edge(perm, edge) {
ir_node *proj = get_edge_src_irn(edge);
const arch_register_t *reg = arch_get_irn_register(aenv, proj);
const arch_register_t *reg = arch_get_irn_register(proj);
DBG((dbg, LEVEL_2, "\tchecking reg of %+F: %s\n", proj, reg ? reg->name : "<none>"));
......@@ -908,7 +907,7 @@ static void assign(ir_node *block, void *env_ptr)
be_lv_foreach(lv, block, be_lv_state_in, idx) {
irn = be_lv_get_irn(lv, block, idx);
if(has_reg_class(env, irn)) {
const arch_register_t *reg = arch_get_irn_register(arch_env, irn);
const arch_register_t *reg = arch_get_irn_register(irn);
int col;
assert(reg && "Node must have been assigned a register");
......@@ -944,13 +943,13 @@ static void assign(ir_node *block, void *env_ptr)
int col = NO_COLOR;
if(ignore || pset_find_ptr(alloc_env->pre_colored, irn)) {
reg = arch_get_irn_register(arch_env, irn);
reg = arch_get_irn_register(irn);
col = reg->index;
assert(!bitset_is_set(colors, col) && "pre-colored register must be free");
} else {
col = get_next_free_reg(alloc_env, colors);
reg = arch_register_for_index(env->cls, col);
assert(arch_get_irn_register(arch_env, irn) == NULL && "This node must not have been assigned a register yet");
assert(arch_get_irn_register(irn) == NULL && "This node must not have been assigned a register yet");
assert(!arch_register_type_is(reg, ignore) && "Must not assign ignore register");
}
......@@ -965,7 +964,7 @@ static void assign(ir_node *block, void *env_ptr)
/* Clear the color upon a use. */
else if(!b->is_def) {
const arch_register_t *reg = arch_get_irn_register(arch_env, irn);
const arch_register_t *reg = arch_get_irn_register(irn);
int col;
assert(reg && "Register must have been assigned");
......
......@@ -274,7 +274,7 @@ static void block_dims_walker(ir_node *block, void *data)
list_for_each_entry_reverse(border_t, b, head, list) {
ir_node *irn = b->irn;
const arch_register_t *reg = arch_get_irn_register(env->arch_env, irn);
const arch_register_t *reg = arch_get_irn_register(irn);
int col = arch_register_get_index(reg);
dims->max_step = MAX(dims->max_step, b->step);
......@@ -397,7 +397,7 @@ static void draw_block(ir_node *bl, void *data)
list_for_each_entry(border_t, b, head, list) {
if (b->is_def) {
const arch_register_t *reg = arch_get_irn_register(env->arch_env, b->irn);
const arch_register_t *reg = arch_get_irn_register(b->irn);
int col = arch_register_get_index(reg);
int live_out = be_is_live_out(lv, bl, b->irn);
int x = (col + 1) * opts->h_inter_gap;
......@@ -425,7 +425,7 @@ static void draw_block(ir_node *bl, void *data)
be_lv_foreach(lv, bl, be_lv_state_in, idx) {
ir_node *irn = be_lv_get_irn(lv, bl, idx);
if (arch_irn_consider_in_reg_alloc(env->arch_env, env->cls, irn)) {
const arch_register_t *reg = arch_get_irn_register(env->arch_env, irn);
const arch_register_t *reg = arch_get_irn_register(irn);
int col = arch_register_get_index(reg);
int x = (col + 1) * opts->h_inter_gap;
color_t color;
......
......@@ -177,7 +177,7 @@ static INLINE int qnode_get_new_color(const qnode_t *qn, ir_node *irn) {
if (found)
return found->new_color;
else
return get_irn_col(qn->ou->co, irn);
return get_irn_col(irn);
}
/**
......@@ -210,7 +210,7 @@ static INLINE void qnode_pin_local(const qnode_t *qn, ir_node *irn) {
node_stat_t *found = qnode_find_or_insert_node(qn, irn);
found->pinned_local = 1;
if (found->new_color == NO_COLOR)
found->new_color = get_irn_col(qn->ou->co, irn);
found->new_color = get_irn_col(irn);
}
......
......@@ -204,7 +204,7 @@ static void *co2_irn_init(ir_phase *ph, const ir_node *irn, void *data)
memset(ci, 0, size);
INIT_LIST_HEAD(&ci->changed_list);
ci->touched_next = env->touched;
ci->orig_col = get_irn_col(env->co, irn);
ci->orig_col = get_irn_col(irn);
env->touched = ci;
ci->irn = irn;
ci->aff = a;
......
......@@ -371,7 +371,7 @@ static void *co_mst_irn_init(ir_phase *ph, const ir_node *irn, void *old) {
res->tmp_col = -1;
res->int_neighs = NULL;
res->int_aff_neigh = 0;
res->col = arch_register_get_index(arch_get_irn_register(env->aenv, irn));
res->col = arch_register_get_index(arch_get_irn_register(irn));
res->init_col = res->col;
INIT_LIST_HEAD(&res->list);
......
......@@ -176,7 +176,7 @@ void sr_reinsert(size_red_t *sr) {
be_ifg_foreach_neighbour(ifg, iter, irn, other) {
if (!sr_is_removed(sr, other)) /* only inspect nodes which are in graph right now */
bitset_set(used_cols, get_irn_col(sr->co, other));
bitset_set(used_cols, get_irn_col(other));
}
/* now all bits not set are possible colors */
......
......@@ -87,7 +87,7 @@ static void build_coloring_cstr(ilp_env_t *ienv) {
bitset_pos_t col;
int cst_idx;
const arch_register_req_t *req;
int curr_node_color = get_irn_col(ienv->co, irn);
int curr_node_color = get_irn_col(irn);
int node_nr = (int)get_irn_idx(irn);
local_env_t *lenv = ienv->env;
......@@ -190,12 +190,12 @@ static void build_affinity_cstr(ilp_env_t *ienv) {
root = curr->nodes[0];
root_nr = (int) get_irn_idx(root);
root_col = get_irn_col(ienv->co, root);
root_col = get_irn_col(root);
for (i = 1; i < curr->node_count; ++i) {
arg = curr->nodes[i];
arg_nr = (int) get_irn_idx(arg);
arg_col = get_irn_col(ienv->co, arg);
arg_col = get_irn_col(arg);
/* add a new affinity variable */
y_idx = lpp_add_var(ienv->lp, name_cdd_sorted(buf, 'y', root_nr, arg_nr), lpp_binary, curr->costs[i]);
......
......@@ -223,7 +223,7 @@ int co_is_optimizable_root(const copy_opt_t *co, ir_node *irn) {
if (arch_irn_is(co->aenv, irn, ignore))
return 0;
reg = arch_get_irn_register(co->aenv, irn);
reg = arch_get_irn_register(irn);
if (arch_register_type_is(reg, ignore))
return 0;
......@@ -650,11 +650,11 @@ int co_get_copy_costs(const copy_opt_t *co) {
ASSERT_OU_AVAIL(co);
list_for_each_entry(unit_t, curr, &co->units, units) {
int root_col = get_irn_col(co, curr->nodes[0]);
int root_col = get_irn_col(curr->nodes[0]);
DBG((dbg, LEVEL_1, " %3d costs for root %+F color %d\n", curr->inevitable_costs, curr->nodes[0], root_col));
res += curr->inevitable_costs;
for (i=1; i<curr->node_count; ++i) {
int arg_col = get_irn_col(co, curr->nodes[i]);
int arg_col = get_irn_col(curr->nodes[i]);
if (root_col != arg_col) {
DBG((dbg, LEVEL_1, " %3d for arg %+F color %d\n", curr->costs[i], curr->nodes[i], arg_col));
res += curr->costs[i];
......@@ -692,7 +692,7 @@ void co_complete_stats(const copy_opt_t *co, co_complete_stats_t *stat)
stat->aff_edges += 1;
stat->max_costs += neigh->costs;
if(get_irn_col(co, an->irn) != get_irn_col(co, neigh->irn)) {
if (get_irn_col(an->irn) != get_irn_col(neigh->irn)) {
stat->costs += neigh->costs;
stat->unsatisfied_edges += 1;
}
......@@ -774,7 +774,7 @@ static void build_graph_walker(ir_node *irn, void *env) {
if (!is_curr_reg_class(co, irn) || arch_irn_is(co->aenv, irn, ignore))
return;
reg = arch_get_irn_register(co->aenv, irn);
reg = arch_get_irn_register(irn);
if (arch_register_type_is(reg, ignore))
return;
......@@ -999,7 +999,7 @@ static int ifg_is_dump_node(void *self, ir_node *irn)
static void ifg_dump_node_attr(FILE *f, void *self, ir_node *irn)
{
co_ifg_dump_t *env = self;
const arch_register_t *reg = arch_get_irn_register(env->co->aenv, irn);
const arch_register_t *reg = arch_get_irn_register(irn);
const arch_register_req_t *req;
int limited;
......@@ -1032,12 +1032,12 @@ static void ifg_dump_at_end(FILE *file, void *self)
affinity_node_t *a;
co_gs_foreach_aff_node(env->co, a) {
const arch_register_t *ar = arch_get_irn_register(env->co->aenv, a->irn);
const arch_register_t *ar = arch_get_irn_register(a->irn);
unsigned aidx = get_irn_idx(a->irn);
neighb_t *n;
co_gs_foreach_neighb(a, n) {
const arch_register_t *nr = arch_get_irn_register(env->co->aenv, n->irn);
const arch_register_t *nr = arch_get_irn_register(n->irn);
unsigned nidx = get_irn_idx(n->irn);
if(aidx < nidx) {
......
......@@ -59,9 +59,9 @@ struct _copy_opt_t {
#define ASSERT_OU_AVAIL(co) assert((co)->units.next && "Representation as optimization-units not build")
#define ASSERT_GS_AVAIL(co) assert((co)->nodes && "Representation as graph not build")
#define get_irn_col(co, irn) arch_register_get_index(arch_get_irn_register((co)->aenv, irn))
#define set_irn_col(co, irn, col) arch_set_irn_register((co)->aenv, irn, arch_register_for_index((co)->cls, col))
#define is_curr_reg_class(co, irn) (arch_get_irn_reg_class(irn, -1) == (co)->cls)
#define get_irn_col(irn) arch_register_get_index(arch_get_irn_register(irn))
#define set_irn_col(co, irn, col) arch_set_irn_register((co)->aenv, irn, arch_register_for_index((co)->cls, col))
#define is_curr_reg_class(co, irn) (arch_get_irn_reg_class(irn, -1) == (co)->cls)
#define list_entry_units(lh) list_entry(lh, unit_t, units)
......
......@@ -451,7 +451,7 @@ static void save_load(ir_node *irn, void *env) {
color_save_t *saver = env;
if (saver->chordal_env->cls == arch_get_irn_reg_class(irn, -1)) {
if (saver->flag == 0) { /* save */
const arch_register_t *reg = arch_get_irn_register(saver->arch_env, irn);
const arch_register_t *reg = arch_get_irn_register(irn);
pmap_insert(saver->saved_colors, irn, (void *) reg);
} else { /*load */
arch_register_t *reg = pmap_get(saver->saved_colors, irn);
......
......@@ -80,10 +80,10 @@ size_t (be_ifg_cliques_iter_size)(const be_ifg_t *ifg)
static void *regs_irn_data_init(ir_phase *ph, const ir_node *irn, void *data)
{
coloring_t *coloring = (coloring_t *) ph;
(void) data;
(void)ph;
(void)data;
return (void *) arch_get_irn_register(coloring->arch_env, irn);
return (void*)arch_get_irn_register(irn);
}
coloring_t *coloring_init(coloring_t *c, ir_graph *irg, const arch_env_t *aenv)
......
......@@ -118,7 +118,7 @@ be_insn_t *be_scan_insn(const be_insn_env_t *env, ir_node *irn)
obstack_grow(obst, &o, sizeof(o));
insn->n_ops++;
insn->out_constraints |= o.has_constraints;
pre_colored += arch_get_irn_register(arch_env, p) != NULL;
pre_colored += arch_get_irn_register(p) != NULL;
}
}
} else if (arch_irn_consider_in_reg_alloc(arch_env, env->cls, irn)) {
......@@ -132,7 +132,7 @@ be_insn_t *be_scan_insn(const be_insn_env_t *env, ir_node *irn)
obstack_grow(obst, &o, sizeof(o));
insn->n_ops++;
insn->out_constraints |= o.has_constraints;
pre_colored += arch_get_irn_register(arch_env, irn) != NULL;
pre_colored += arch_get_irn_register(irn) != NULL;
}
if (pre_colored > 0) {
......
......@@ -124,7 +124,7 @@ ir_node *insert_Perm_after(be_irg_t *birg,
curr = perm;
for (i = 0; i < n; ++i) {
ir_node *perm_op = get_irn_n(perm, i);
const arch_register_t *reg = arch_get_irn_register(arch_env, perm_op);
const arch_register_t *reg = arch_get_irn_register(perm_op);
be_ssa_construction_env_t senv;
ir_mode *mode = get_irn_mode(perm_op);
......
......@@ -314,7 +314,7 @@ static void lower_perm_node(ir_node *irn, void *walk_env) {
n = get_irn_arity(irn);
assert(n == get_irn_n_edges(irn) && "perm's in and out numbers different");
reg_class = arch_get_irn_register(arch_env, get_irn_n(irn, 0))->reg_class;
reg_class = arch_get_irn_register(get_irn_n(irn, 0))->reg_class;
pairs = alloca(n * sizeof(pairs[0]));
/* build the list of register pairs (in, out) */
......@@ -324,8 +324,8 @@ static void lower_perm_node(ir_node *irn, void *walk_env) {
pn = get_Proj_proj(pairs[i].out_node);
pairs[i].in_node = get_irn_n(irn, pn);
pairs[i].in_reg = arch_get_irn_register(arch_env, pairs[i].in_node);
pairs[i].out_reg = arch_get_irn_register(arch_env, pairs[i].out_node);
pairs[i].in_reg = arch_get_irn_register(pairs[i].in_node);
pairs[i].out_reg = arch_get_irn_register(pairs[i].out_node);
pairs[i].checked = 0;
i++;
......@@ -974,7 +974,7 @@ found_front:
sched_add_after(perm, node);
/* give it the proj's register */
arch_set_irn_register(aenv, node, arch_get_irn_register(aenv, proj));
arch_set_irn_register(aenv, node, arch_get_irn_register(proj));
/* reroute all users of the proj to the moved node. */
edges_reroute(proj, node, irg);
......
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