Commit d64ea79e authored by Christoph Mallon's avatar Christoph Mallon
Browse files

Remove the unused parameter const arch_env_t *env from arch_get_register_req().

[r22676]
parent 4a3629a5
......@@ -91,10 +91,7 @@ static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
/* in case of a joker register: just return a valid register */
if (arch_register_type_is(reg, joker)) {
const arch_register_req_t *req;
/* ask for the requirements */
req = arch_get_register_req(arch_env, irn, pos);
const arch_register_req_t *req = arch_get_register_req(irn, pos);
if (arch_register_req_is(req, limited)) {
/* in case of limited requirements: get the first allowed register */
......
......@@ -84,11 +84,9 @@ static INLINE const arch_irn_ops_t *get_irn_ops(const ir_node *irn)
return be_ops;
}
const arch_register_req_t *arch_get_register_req(const arch_env_t *env,
const ir_node *irn, int pos)
const arch_register_req_t *arch_get_register_req(const ir_node *irn, int pos)
{
const arch_irn_ops_t *ops = get_irn_ops(irn);
(void)env; // TODO remove parameter
return ops->get_irn_reg_req(irn, pos);
}
......@@ -221,9 +219,8 @@ int arch_is_register_operand(const arch_env_t *env,
int arch_reg_is_allocatable(const arch_env_t *env, const ir_node *irn,
int pos, const arch_register_t *reg)
{
const arch_register_req_t *req;
req = arch_get_register_req(env, irn, pos);
const arch_register_req_t *req = arch_get_register_req(irn, pos);
(void)env; // TODO remove parameter
if(req->type == arch_register_req_type_none)
return 0;
......
......@@ -146,14 +146,12 @@ extern void arch_perform_memory_operand(const arch_env_t *env, ir_node *irn, ir_
/**
* Get the register requirements for a node.
* @param env The architecture environment.
* @param irn The node.
* @param pos The position of the operand you're interested in.
* @return A pointer to the register requirements. If NULL is returned, the
* operand was no register operand.
*/
extern const arch_register_req_t *
arch_get_register_req(const arch_env_t *env, const ir_node *irn, int pos);
const arch_register_req_t *arch_get_register_req(const ir_node *irn, int pos);
/**
* Check if an operand is a register operand.
......
......@@ -182,9 +182,6 @@ static INLINE int has_reg_class(const be_chordal_env_t *env, const ir_node *irn)
return arch_irn_consider_in_reg_alloc(env->birg->main_env->arch_env, env->cls, irn);
}
#define has_limited_constr(req, irn) \
(arch_get_register_req(arch_env, (req), irn, -1) && (req)->type == arch_register_req_type_limited)
static int get_next_free_reg(const be_chordal_alloc_env_t *alloc_env, bitset_t *colors)
{
bitset_t *tmp = alloc_env->tmp_colors;
......@@ -258,7 +255,7 @@ static ir_node *prepare_constr_insn(be_chordal_env_t *env, ir_node *irn)
if(arch_register_type_is(reg, joker))
continue;
req = arch_get_register_req(aenv, irn, i);
req = arch_get_register_req(irn, i);
if (!arch_register_req_is(req, limited))
continue;
......
......@@ -242,7 +242,6 @@ static ir_node *qnode_color_irn(const qnode_t *qn, ir_node *irn, int col, const
copy_opt_t *co = qn->ou->co;
const be_chordal_env_t *chordal_env = co->cenv;
const arch_register_class_t *cls = co->cls;
const arch_env_t *arch_env = co->aenv;
int irn_col = qnode_get_new_color(qn, irn);
ir_node *sub_res, *curr;
be_ifg_t *ifg = chordal_env->ifg;
......@@ -278,7 +277,7 @@ static ir_node *qnode_color_irn(const qnode_t *qn, ir_node *irn, int col, const
bitset_flip_all(free_cols);
/* Exclude colors not assignable to the irn */
req = arch_get_register_req(arch_env, irn, -1);
req = arch_get_register_req(irn, -1);
if (arch_register_req_is(req, limited)) {
bitset_t *limited = bitset_alloca(cls->n_regs);
rbitset_copy_to_bitset(req->limited, limited);
......@@ -302,7 +301,7 @@ static ir_node *qnode_color_irn(const qnode_t *qn, ir_node *irn, int col, const
#endif /* SEARCH_FREE_COLORS */
/* If target color is not allocatable changing color is impossible */
if (!arch_reg_is_allocatable(arch_env, irn, -1, arch_register_for_index(cls, col))) {
if (!arch_reg_is_allocatable(co->aenv, irn, -1, arch_register_for_index(cls, col))) {
DBG((dbg, LEVEL_3, "\t %+F impossible\n", irn));
return CHANGE_IMPOSSIBLE;
}
......
......@@ -266,7 +266,7 @@ static INLINE bitset_t *get_adm(co2_t *env, co2_irn_t *ci)
if(ci->adm_cache == NULL) {
const arch_register_req_t *req;
ci->adm_cache = bitset_obstack_alloc(phase_obst(&env->ph), env->n_regs);
req = arch_get_register_req(env->co->aenv, ci->irn, BE_OUT_POS(0));
req = arch_get_register_req(ci->irn, BE_OUT_POS(0));
if(arch_register_req_is(req, limited)) {
int i, n;
......@@ -309,7 +309,7 @@ static void incur_constraint_costs(co2_t *env, const ir_node *irn, col_cost_pair
{
const arch_register_req_t *req;
req = arch_get_register_req(env->co->aenv, irn, BE_OUT_POS(0));
req = arch_get_register_req(irn, BE_OUT_POS(0));
if (arch_register_req_is(req, limited)) {
unsigned n_regs = env->co->cls->n_regs;
......@@ -1154,11 +1154,11 @@ static const char *get_dot_color_name(size_t col)
return col < (sizeof(names)/sizeof(names[0])) ? names[col] : "white";
}
static const char *get_dot_shape_name(co2_t *env, co2_irn_t *ci)
static const char *get_dot_shape_name(co2_irn_t *ci)
{
const arch_register_req_t *req;
req = arch_get_register_req(env->co->aenv, ci->irn, BE_OUT_POS(0));
req = arch_get_register_req(ci->irn, BE_OUT_POS(0));
if(arch_register_req_is(req, limited))
return "diamond";
......@@ -1201,7 +1201,7 @@ static void ifg_dump_node_attr(FILE *f, void *self, ir_node *irn)
}
ir_fprintf(f, "label=\"%+F%s\" style=filled peripheries=%d color=%s shape=%s", irn, buf, peri,
get_dot_color_name(get_col(env, irn)), get_dot_shape_name(env, ci));
get_dot_color_name(get_col(env, irn)), get_dot_shape_name(ci));
}
static void ifg_dump_at_end(FILE *file, void *self)
......
......@@ -381,7 +381,7 @@ static void *co_mst_irn_init(ir_phase *ph, const ir_node *irn, void *old) {
res->adm_colors = bitset_obstack_alloc(phase_obst(ph), env->n_regs);
/* Exclude colors not assignable to the irn */
req = arch_get_register_req(env->aenv, irn, -1);
req = arch_get_register_req(irn, -1);
if (arch_register_req_is(req, limited))
rbitset_copy_to_bitset(req->limited, res->adm_colors);
else
......
......@@ -140,9 +140,7 @@ void sr_remove(size_red_t *sr) {
while (redo) {
redo = 0;
be_ifg_foreach_node(ifg, iter, irn) {
const arch_register_req_t *req;
req = arch_get_register_req(sr->co->aenv, irn, -1);
const arch_register_req_t *req = arch_get_register_req(irn, -1);
if (!arch_register_req_is(req, limited) && !sr_is_removed(sr, irn) && !co_gs_is_optimizable(sr->co, irn)) {
if (sr_is_simplicial(sr, irn)) {
......
......@@ -93,7 +93,7 @@ static void build_coloring_cstr(ilp_env_t *ienv) {
pmap_insert(lenv->nr_2_irn, INT_TO_PTR(node_nr), irn);
req = arch_get_register_req(ienv->co->aenv, irn, -1);
req = arch_get_register_req(irn, -1);
bitset_clear_all(colors);
......
......@@ -228,7 +228,7 @@ int co_is_optimizable_root(const copy_opt_t *co, ir_node *irn) {
if (arch_register_type_is(reg, ignore))
return 0;
req = arch_get_register_req(co->aenv, irn, -1);
req = arch_get_register_req(irn, -1);
if (is_Reg_Phi(irn) || is_Perm_Proj(co->aenv, irn) || is_2addr_code(req))
return 1;
......@@ -449,8 +449,7 @@ static void co_collect_units(ir_node *irn, void *env) {
unit->nodes[1] = get_Perm_src(irn);
unit->costs[1] = co->get_costs(co, irn, unit->nodes[1], -1);
} else {
const arch_register_req_t *req =
arch_get_register_req(co->aenv, irn, -1);
const arch_register_req_t *req = arch_get_register_req(irn, -1);
/* Src == Tgt of a 2-addr-code instruction */
if (is_2addr_code(req)) {
......@@ -523,12 +522,11 @@ static int compare_ous(const void *k1, const void *k2) {
const unit_t *u2 = *((const unit_t **) k2);
int i, o, u1_has_constr, u2_has_constr;
arch_register_req_t req;
const arch_env_t *aenv = u1->co->aenv;
/* Units with constraints come first */
u1_has_constr = 0;
for (i=0; i<u1->node_count; ++i) {
arch_get_register_req(aenv, &req, u1->nodes[i], -1);
arch_get_register_req(&req, u1->nodes[i], -1);
if (arch_register_req_is(&req, limited)) {
u1_has_constr = 1;
break;
......@@ -537,7 +535,7 @@ static int compare_ous(const void *k1, const void *k2) {
u2_has_constr = 0;
for (i=0; i<u2->node_count; ++i) {
arch_get_register_req(aenv, &req, u2->nodes[i], -1);
arch_get_register_req(&req, u2->nodes[i], -1);
if (arch_register_req_is(&req, limited)) {
u2_has_constr = 1;
break;
......@@ -792,7 +790,7 @@ static void build_graph_walker(ir_node *irn, void *env) {
add_edges(co, irn, arg, co->get_costs(co, irn, arg, 0));
}
else { /* 2-address code */
const arch_register_req_t *req = arch_get_register_req(co->aenv, irn, -1);
const arch_register_req_t *req = arch_get_register_req(irn, -1);
if (is_2addr_code(req)) {
const unsigned other = req->other_same;
int i;
......@@ -849,7 +847,7 @@ static int co_dump_appel_disjoint_constraints(const copy_opt_t *co, ir_node *a,
constr[1] = bitset_alloca(co->cls->n_regs);
for (j = 0; j < 2; ++j) {
req = arch_get_register_req(co->aenv, nodes[j], BE_OUT_POS(0));
req = arch_get_register_req(nodes[j], BE_OUT_POS(0));
if(arch_register_req_is(req, limited))
rbitset_copy_to_bitset(req->limited, constr[j]);
else
......@@ -901,7 +899,7 @@ void co_dump_appel_graph(const copy_opt_t *co, FILE *f)
const arch_register_req_t *req;
ir_node *adj;
req = arch_get_register_req(co->aenv, irn, BE_OUT_POS(0));
req = arch_get_register_req(irn, BE_OUT_POS(0));
if(arch_register_req_is(req, limited)) {
for(i = 0; i < co->cls->n_regs; ++i) {
if(!rbitset_is_set(req->limited, i) && color_map[i] >= 0)
......@@ -1006,7 +1004,7 @@ static void ifg_dump_node_attr(FILE *f, void *self, ir_node *irn)
const arch_register_req_t *req;
int limited;
req = arch_get_register_req(env->co->aenv, irn, BE_OUT_POS(0));
req = arch_get_register_req(irn, BE_OUT_POS(0));
limited = arch_register_req_is(req, limited);
if(env->flags & CO_IFG_DUMP_LABELS) {
......
......@@ -59,7 +59,7 @@ static void add_machine_operands(const be_insn_env_t *env, be_insn_t *insn, ir_n
be_operand_t o;
/* found a register use, create an operand */
o.req = arch_get_register_req(arch_env, mach_op, i);
o.req = arch_get_register_req(mach_op, i);
o.carrier = op;
o.irn = insn->irn;
o.pos = i;
......@@ -109,7 +109,7 @@ be_insn_t *be_scan_insn(const be_insn_env_t *env, ir_node *irn)
if (arch_irn_consider_in_reg_alloc(arch_env, env->cls, p)) {
/* found a def: create a new operand */
o.req = arch_get_register_req(arch_env, p, -1);
o.req = arch_get_register_req(p, -1);
o.carrier = p;
o.irn = irn;
o.pos = -(get_Proj_proj(p) + 1);
......@@ -123,7 +123,7 @@ be_insn_t *be_scan_insn(const be_insn_env_t *env, ir_node *irn)
}
} else if (arch_irn_consider_in_reg_alloc(arch_env, env->cls, irn)) {
/* only one def, create one operand */
o.req = arch_get_register_req(arch_env, irn, -1);
o.req = arch_get_register_req(irn, -1);
o.carrier = irn;
o.irn = irn;
o.pos = -1;
......@@ -149,7 +149,7 @@ be_insn_t *be_scan_insn(const be_insn_env_t *env, ir_node *irn)
add_machine_operands(env, insn, op);
} else if (arch_irn_consider_in_reg_alloc(arch_env, env->cls, op)) {
/* found a register use, create an operand */
o.req = arch_get_register_req(arch_env, irn, i);
o.req = arch_get_register_req(irn, i);
o.carrier = op;
o.irn = irn;
o.pos = i;
......
......@@ -617,11 +617,8 @@ static void gen_assure_different_pattern(ir_node *irn, ir_node *other_different,
* then to assure the constraint.
*/
static void assure_different_constraints(ir_node *irn, constraint_env_t *env) {
const arch_register_req_t *req;
const arch_env_t *arch_env = be_get_birg_arch_env(env->birg);
ir_node *skipped_irn = belower_skip_proj(irn);
req = arch_get_register_req(arch_env, irn, -1);
const arch_register_req_t *req = arch_get_register_req(irn, -1);
if (arch_register_req_is(req, must_be_different)) {
const unsigned other = req->other_different;
......@@ -955,10 +952,10 @@ found_front:
if(arch_irn_is(aenv, node, modify_flags))
break;
if(is_Proj(node)) {
req = arch_get_register_req(aenv, get_Proj_pred(node),
req = arch_get_register_req(get_Proj_pred(node),
-1 - get_Proj_proj(node));
} else {
req = arch_get_register_req(aenv, node, -1);
req = arch_get_register_req(node, -1);
}
if(req->type != arch_register_req_type_normal)
break;
......
......@@ -1315,7 +1315,7 @@ const arch_register_req_t *get_Phi_reg_req_recursive(const ir_node *phi,
/* Matze: don't we unnecessary constraint our phis with this?
* we only need to take the regclass IMO*/
if(!is_Phi(op))
return arch_get_register_req(phi_handler.arch_env, op, BE_OUT_POS(0));
return arch_get_register_req(op, BE_OUT_POS(0));
}
/*
......
......@@ -183,9 +183,8 @@ ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
*/
static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos)
{
const arch_register_req_t *req;
const arch_register_req_t *req = arch_get_register_req(irn, pos);
req = arch_get_register_req(cg->arch_env, irn, pos);
assert(req != NULL && "Missing register requirements");
if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
return ia32_new_NoReg_gp(cg);
......
......@@ -138,10 +138,7 @@ static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
/* in case of unknown register: just return a valid register */
if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
const arch_register_req_t *req;
/* ask for the requirements */
req = arch_get_register_req(arch_env, irn, pos);
const arch_register_req_t *req = arch_get_register_req(irn, pos);
if (arch_register_req_is(req, limited)) {
/* in case of limited requirements: get the first allowed register */
......
......@@ -4276,8 +4276,7 @@ static ir_node *gen_be_Call(ir_node *node)
i = get_irn_arity(node) - 1;
fpcw = be_transform_node(get_irn_n(node, i--));
for (; i >= be_pos_Call_first_arg; --i) {
arch_register_req_t const *const req =
arch_get_register_req(env_cg->arch_env, node, i);
arch_register_req_t const *const req = arch_get_register_req(node, i);
ir_node *const reg_parm = be_transform_node(get_irn_n(node, i));
assert(req->type == arch_register_req_type_limited);
......@@ -4402,7 +4401,7 @@ static ir_node *gen_Proj_be_Call(ir_node *node)
} else if (proj == pn_be_Call_M_regular) {
proj = pn_ia32_Call_M;
} else {
arch_register_req_t const *const req = arch_get_register_req(env_cg->arch_env, node, BE_OUT_POS(proj));
arch_register_req_t const *const req = arch_get_register_req(node, BE_OUT_POS(proj));
int const n_outs = get_ia32_n_res(new_call);
int i;
......
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