Commit d7c7997f authored by Christoph Mallon's avatar Christoph Mallon
Browse files

ia32: Unify creation of Immediates.

* Provide a function for a full Immediate (entity + constant) and one for just a constant
* Place all immediates in the start block
* This slightly reduces the inconsistency, that some constant-only Immediates had no_pic_adjust set
parent d6f71b4d
......@@ -102,14 +102,11 @@ ir_entity *ia32_create_float_const_entity(ia32_isa_t *isa, ir_tarval *tv,
return res;
}
ir_node *ia32_create_Immediate(ir_graph *const irg, ir_entity *const entity,
long const val)
ir_node *ia32_create_Immediate_full(ir_graph *const irg, ir_entity *const entity, bool const no_pic_adjust, int32_t const val)
{
ir_node *start_block = get_irg_start_block(irg);
ir_node *immediate = new_bd_ia32_Immediate(NULL, start_block, entity,
ia32_no_pic_adjust, val);
ir_node *const start_block = get_irg_start_block(irg);
ir_node *const immediate = new_bd_ia32_Immediate(NULL, start_block, entity, no_pic_adjust, val);
arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
return immediate;
}
......@@ -824,5 +821,5 @@ ir_node *ia32_try_create_Immediate(ir_node *node, char immediate_constraint_type
}
ir_graph *const irg = get_irn_irg(node);
return ia32_create_Immediate(irg, entity, val);
return ia32_create_Immediate_full(irg, entity, ia32_no_pic_adjust, val);
}
......@@ -28,13 +28,24 @@ ir_entity *ia32_create_float_const_entity(ia32_isa_t *isa, ir_tarval *tv,
ident *name);
/**
* Creates an immediate.
* Create an immediate.
*
* @param irg The IR graph the node belongs to.
* @param entity if set, entity for the immediate
* @param val integer value for the immediate
*/
ir_node *ia32_create_Immediate(ir_graph *irg, ir_entity *entity, long val);
ir_node *ia32_create_Immediate_full(ir_graph *irg, ir_entity *entity, bool no_pic_adjust, int32_t val);
/**
* Create an immediate.
*
* @param irg The IR graph the node belongs to.
* @param val integer value for the immediate
*/
static inline ir_node *ia32_create_Immediate(ir_graph *const irg, int32_t const val)
{
return ia32_create_Immediate_full(irg, NULL, false, val);
}
/**
* returns register by name (used for determining clobber specifications in
......
......@@ -17,7 +17,7 @@
#include "ia32_fpu.h"
#include "ia32_new_nodes.h"
#include "ia32_architecture.h"
#include "ia32_optimize.h"
#include "ia32_common_transform.h"
#include "gen_ia32_regalloc_if.h"
#include "ircons.h"
......@@ -122,7 +122,7 @@ static ir_node *create_fpu_mode_reload(void *const env, ir_node *const state, ir
ir_node *const load_res = new_r_Proj(load, ia32_mode_gp, pn_ia32_Load_res);
/* TODO: Make the actual mode configurable in ChangeCW. */
ir_node *const or_const = ia32_immediate_from_long(irg, 0xC00);
ir_node *const or_const = ia32_create_Immediate(irg, 0xC00);
ir_node *const orn = new_bd_ia32_Or(NULL, block, noreg, noreg, nomem, load_res, or_const);
sched_add_before(before, orn);
......
......@@ -282,15 +282,15 @@ static void peephole_ia32_Test(ir_node *node)
if ((offset & 0xFFFFFF80) == 0) {
/* attr->am_offs += 0; */
} else if ((offset & 0xFFFF80FF) == 0) {
ir_node *imm_node = ia32_create_Immediate(irg, NULL, offset >> 8);
ir_node *const imm_node = ia32_create_Immediate(irg, offset >> 8);
set_irn_n(node, n_ia32_Test_right, imm_node);
attr->am_offs += 1;
} else if ((offset & 0xFF80FFFF) == 0) {
ir_node *imm_node = ia32_create_Immediate(irg, NULL, offset >> 16);
ir_node *const imm_node = ia32_create_Immediate(irg, offset >> 16);
set_irn_n(node, n_ia32_Test_right, imm_node);
attr->am_offs += 2;
} else if ((offset & 0x00FFFFFF) == 0) {
ir_node *imm_node = ia32_create_Immediate(irg, NULL, offset >> 24);
ir_node *const imm_node = ia32_create_Immediate(irg, offset >> 24);
set_irn_n(node, n_ia32_Test_right, imm_node);
attr->am_offs += 3;
} else {
......@@ -739,28 +739,6 @@ static inline int is_noreg(const ir_node *node)
return is_ia32_NoReg_GP(node);
}
ir_node *ia32_immediate_from_long(ir_graph *const irg, long const val)
{
ir_node *start_block = get_irg_start_block(irg);
ir_node *immediate = new_bd_ia32_Immediate(NULL, start_block, NULL, 0, val);
arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
return immediate;
}
static ir_node *create_immediate_from_am(const ir_node *node)
{
ir_node *block = get_nodes_block(node);
int offset = get_ia32_am_offs_int(node);
const ia32_attr_t *attr = get_ia32_attr_const(node);
int sc_no_pic_adjust = attr->am_sc_no_pic_adjust;
ir_entity *entity = get_ia32_am_ent(node);
ir_node *res = new_bd_ia32_Immediate(NULL, block, entity, sc_no_pic_adjust, offset);
arch_set_irn_register(res, &ia32_registers[REG_GP_NOREG]);
return res;
}
static bool is_disp_const(ir_node const *const node, int32_t const val)
{
return !get_ia32_am_ent(node) && get_ia32_am_offs_int(node) == val;
......@@ -826,7 +804,9 @@ static void peephole_ia32_Lea(ir_node *node)
goto exchange;
}
}
op2 = create_immediate_from_am(node);
ir_graph *const irg = get_irn_irg(node);
ia32_attr_t const *const attr = get_ia32_attr_const(node);
op2 = ia32_create_Immediate_full(irg, attr->am_ent, attr->am_sc_no_pic_adjust, attr->am_offs);
} else if (has_disp) {
return; /* Lea has base, index and displacement. */
}
......@@ -844,7 +824,7 @@ static void peephole_ia32_Lea(ir_node *node)
dbg_info *const dbgi = get_irn_dbg_info(node);
ir_node *const block = get_nodes_block(node);
ir_graph *const irg = get_irn_irg(node);
ir_node *const amt = ia32_immediate_from_long(irg, scale);
ir_node *const amt = ia32_create_Immediate(irg, scale);
res = new_bd_ia32_Shl(dbgi, block, op1, amt);
} else {
return; /* Lea has scaled index as well as base and/or displacement. */
......
......@@ -35,9 +35,4 @@ void ia32_peephole_optimization(ir_graph *irg);
/** Initialize the ia32 address mode optimizer. */
void ia32_init_optimize(void);
/**
* Creates an immediate node.
*/
ir_node *ia32_immediate_from_long(ir_graph *irg, long val);
#endif
......@@ -44,7 +44,6 @@
#include "ia32_common_transform.h"
#include "ia32_new_nodes.h"
#include "ia32_nodes_attr.h"
#include "ia32_optimize.h"
#include "ia32_transform.h"
#include "util.h"
#include "x86_address_mode.h"
......@@ -234,8 +233,8 @@ static ir_node *gen_Const(ir_node *node)
#ifdef CONSTRUCT_SSE_CONST
} else if (tarval_is_one(tv)) {
int cnst = mode == ia32_mode_float32 ? 26 : 55;
ir_node *imm1 = ia32_create_Immediate(irg, NULL, cnst);
ir_node *imm2 = ia32_create_Immediate(irg, NULL, 2);
ir_node *imm1 = ia32_create_Immediate(irg, cnst);
ir_node *imm2 = ia32_create_Immediate(irg, 2);
ir_node *pslld, *psrld;
load = new_bd_ia32_xAllOnes(dbgi, block);
......@@ -264,7 +263,7 @@ static ir_node *gen_Const(ir_node *node)
(get_tarval_sub_bits(tv, 2) << 16) |
(get_tarval_sub_bits(tv, 3) << 24);
if (val == 0) {
ir_node *imm32 = ia32_create_Immediate(irg, NULL, 32);
ir_node *imm32 = ia32_create_Immediate(irg, 32);
ir_node *cnst, *psllq;
/* fine, lower 32bit are zero, produce 32bit value */
......@@ -1725,7 +1724,7 @@ static ir_node *create_sex_32_64(dbg_info *dbgi, ir_node *block,
res = new_bd_ia32_Cltd(dbgi, block, val, pval);
} else {
ir_graph *const irg = get_irn_irg(block);
ir_node *const imm31 = ia32_create_Immediate(irg, NULL, 31);
ir_node *const imm31 = ia32_create_Immediate(irg, 31);
res = new_bd_ia32_Sar(dbgi, block, val, imm31);
}
SET_IA32_ORIG_NODE(res, orig);
......@@ -2674,7 +2673,7 @@ static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns)
panic("invalid size of Store float to mem (%+F)", node);
}
ir_graph *const irg = get_irn_irg(new_block);
ir_node *const imm = ia32_create_Immediate(irg, NULL, val);
ir_node *const imm = ia32_create_Immediate(irg, val);
ir_node *new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
addr.index, addr.mem, imm);
......@@ -3627,7 +3626,7 @@ static ir_node *gen_Mux(ir_node *node)
case SETCC_TR_SHL: {
ir_graph *const irg = get_irn_irg(new_block);
ir_node *const imm = ia32_immediate_from_long(irg, res.steps[step].scale);
ir_node *const imm = ia32_create_Immediate(irg, res.steps[step].scale);
SET_IA32_ORIG_NODE(imm, node);
new_node = new_bd_ia32_Shl(dbgi, new_block, new_node, imm);
SET_IA32_ORIG_NODE(new_node, node);
......@@ -3646,7 +3645,7 @@ static ir_node *gen_Mux(ir_node *node)
case SETCC_TR_AND: {
ir_graph *const irg = get_irn_irg(new_block);
ir_node *const imm = ia32_immediate_from_long(irg, res.steps[step].val);
ir_node *const imm = ia32_create_Immediate(irg, res.steps[step].val);
SET_IA32_ORIG_NODE(imm, node);
new_node = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, imm);
SET_IA32_ORIG_NODE(new_node, node);
......@@ -3659,7 +3658,7 @@ static ir_node *gen_Mux(ir_node *node)
case SETCC_TR_OR: {
ir_graph *const irg = get_irn_irg(new_block);
ir_node *const imm = ia32_immediate_from_long(irg, res.steps[step].val);
ir_node *const imm = ia32_create_Immediate(irg, res.steps[step].val);
SET_IA32_ORIG_NODE(imm, node);
new_node = new_bd_ia32_Or(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, imm);
SET_IA32_ORIG_NODE(new_node, node);
......@@ -3807,7 +3806,7 @@ static void store_gp(dbg_info *dbgi, ia32_address_mode_t *am, ir_node *block,
if (!mode_is_signed(mode) && extend_unsigned) {
ir_node *in[2];
/* store a zero */
ir_node *zero_const = ia32_create_Immediate(irg, NULL, 0);
ir_node *zero_const = ia32_create_Immediate(irg, 0);
ir_node *zero_store = new_bd_ia32_Store(dbgi, new_block, frame,
noreg_GP, nomem, zero_const);
......@@ -4530,7 +4529,7 @@ static ir_node *gen_ia32_l_LLtoFloat(ir_node *node)
ir_node *res = new_r_Proj(fild, mode_fp, pn_ia32_fild_res);
if (!mode_is_signed(get_irn_mode(val_high))) {
ir_node *count = ia32_create_Immediate(irg, NULL, 31);
ir_node *const count = ia32_create_Immediate(irg, 31);
ia32_address_mode_t am;
am.addr.base = get_global_base(irg);
......@@ -5260,7 +5259,7 @@ static ir_node *gen_clz(ir_node *node)
dbg_info *dbgi = get_irn_dbg_info(real);
ir_node *block = get_nodes_block(real);
ir_graph *irg = get_irn_irg(block);
ir_node *imm = ia32_create_Immediate(irg, NULL, 31);
ir_node *imm = ia32_create_Immediate(irg, 31);
return new_bd_ia32_Xor(dbgi, block, noreg_GP, noreg_GP, nomem, bsr, imm);
}
......@@ -5290,7 +5289,7 @@ static ir_node *gen_parity(ir_node *node)
* chance for CSE, constant folding and other goodies for some of these
* operations) */
ir_graph *const irg = get_irn_irg(new_block);
ir_node *const count = ia32_create_Immediate(irg, NULL, 16);
ir_node *const count = ia32_create_Immediate(irg, 16);
ir_node *const shr = new_bd_ia32_Shr(dbgi, new_block, new_param, count);
ir_node *const xorn = new_bd_ia32_Xor(dbgi, new_block, noreg_GP,
noreg_GP, nomem, shr, new_param);
......@@ -5359,9 +5358,9 @@ static ir_node *gen_bswap(ir_node *node)
return new_bd_ia32_Bswap(dbgi, new_block, param);
} else {
ir_graph *const irg = get_irn_irg(new_block);
ir_node *const i8 = ia32_create_Immediate(irg, NULL, 8);
ir_node *const i8 = ia32_create_Immediate(irg, 8);
ir_node *const rol1 = new_bd_ia32_Rol(dbgi, new_block, param, i8);
ir_node *const i16 = ia32_create_Immediate(irg, NULL, 16);
ir_node *const i16 = ia32_create_Immediate(irg, 16);
ir_node *const rol2 = new_bd_ia32_Rol(dbgi, new_block, rol1, i16);
ir_node *const rol3 = new_bd_ia32_Rol(dbgi, new_block, rol2, i8);
set_ia32_ls_mode(rol1, mode_Hu);
......@@ -5422,7 +5421,7 @@ static ir_node *gen_saturating_increment(ir_node *node)
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *operand = be_transform_node(get_Builtin_param(node, 0));
ir_graph *irg = get_irn_irg(block);
ir_node *one = ia32_create_Immediate(irg, NULL, 1);
ir_node *one = ia32_create_Immediate(irg, 1);
ir_node *increment = new_bd_ia32_Add(dbgi, block, noreg_GP, noreg_GP,
nomem, operand, one);
set_irn_mode(increment, mode_T);
......@@ -5434,7 +5433,7 @@ static ir_node *gen_saturating_increment(ir_node *node)
ir_node *value = new_rd_Proj(dbgi, increment, ia32_mode_gp, pn_ia32_Add_res);
ir_node *eflags = new_rd_Proj(dbgi, increment, ia32_mode_gp, pn_ia32_Add_flags);
ir_node *zero = ia32_create_Immediate(irg, NULL, 0);
ir_node *zero = ia32_create_Immediate(irg, 0);
ir_node *sbb = new_bd_ia32_Sbb(dbgi, block, noreg_GP, noreg_GP, nomem,
value, zero, eflags);
set_ia32_ls_mode(sbb, ia32_mode_gp);
......
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