Commit da38cf48 authored by Matthias Braun's avatar Matthias Braun
Browse files

normalize x+x to x << 1 in later compiler phases

Also added a new matcher for the ia32 backend matching Shl(x,1) to
Lea(x,x).
parent 9ebabcf3
......@@ -1764,6 +1764,19 @@ static ir_node *gen_Shl(ir_node *node)
ir_node *left = get_Shl_left(node);
ir_node *right = get_Shl_right(node);
/* special case Shl x,1 => Lea x,x because Lea has fewer register
* constraints */
if (is_Const_1(right)) {
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
ir_node *new_left = be_transform_node(left);
ir_node *new_node
= new_bd_ia32_Lea(dbgi, new_block, new_left, new_left);
SET_IA32_ORIG_NODE(new_node, node);
return new_node;
}
return gen_shift_binop(node, left, right, new_bd_ia32_Shl,
match_mode_neutral | match_immediate);
}
......
......@@ -2364,8 +2364,8 @@ static ir_node *transform_node_Add(ir_node *n)
ir_graph *irg = get_irn_irg(n);
/* the following code leads to endless recursion when Mul are replaced
* by a simple instruction chain */
if (!irg_is_constrained(irg, IR_GRAPH_CONSTRAINT_ARCH_DEP)
&& a == b && mode_is_int(mode)) {
if (a == b) {
if (!irg_is_constrained(irg, IR_GRAPH_CONSTRAINT_ARCH_DEP)) {
ir_node *block = get_nodes_block(n);
n = new_rd_Mul(
......@@ -2376,6 +2376,13 @@ static ir_node *transform_node_Add(ir_node *n)
mode);
DBG_OPT_ALGSIM0(oldn, n, FS_OPT_ADD_A_A);
return n;
} else {
dbg_info *dbgi = get_irn_dbg_info(n);
ir_node *block = get_nodes_block(n);
ir_node *one = new_r_Const(irg, get_mode_one(mode_Iu));
n = new_rd_Shl(dbgi, block, a, one, mode);
return n;
}
}
if (is_Minus(a)) {
n = new_rd_Sub(
......
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