Commit e3c7024e authored by Christoph Mallon's avatar Christoph Mallon
Browse files

ia32: Invert the sense of '#' in ia32_emitf() when emitting registers.

Now the ls_mode is respected by default, wich is more sensible, and '#' is used to emit a 32 bit register.
parent a1daf895
......@@ -343,12 +343,12 @@ void x86_emit_condition_code(x86_condition_code_t cc)
typedef enum ia32_emit_mod_t {
EMIT_NONE = 0,
EMIT_RESPECT_LS = 1U << 0,
EMIT_ALTERNATE_AM = 1U << 1,
EMIT_LONG = 1U << 2,
EMIT_ALTERNATE_AM = 1U << 0,
EMIT_LONG = 1U << 1,
EMIT_LOW_REG = 1U << 2,
EMIT_HIGH_REG = 1U << 3,
EMIT_LOW_REG = 1U << 4,
EMIT_16BIT_REG = 1U << 5,
EMIT_16BIT_REG = 1U << 4,
EMIT_32BIT_REG = 1U << 5,
EMIT_SHIFT_COMMA = 1U << 6,
} ia32_emit_mod_t;
ENUM_BITSET(ia32_emit_mod_t)
......@@ -444,11 +444,11 @@ void ia32_emitf(ir_node const *const node, char const *fmt, ...)
for (;;) {
switch (*fmt) {
case '*': mod |= EMIT_ALTERNATE_AM; break;
case '#': mod |= EMIT_RESPECT_LS; break;
case 'l': mod |= EMIT_LONG; break;
case '>': mod |= EMIT_HIGH_REG; break;
case '<': mod |= EMIT_LOW_REG; break;
case '>': mod |= EMIT_HIGH_REG; break;
case '^': mod |= EMIT_16BIT_REG; break;
case '#': mod |= EMIT_32BIT_REG; break;
case ',': mod |= EMIT_SHIFT_COMMA; break;
default:
goto end_of_mods;
......@@ -600,7 +600,7 @@ emit_I:
ir_mode *mode = get_ia32_ls_mode(node);
if (!mode)
mode = ia32_mode_gp;
if (mod & EMIT_RESPECT_LS) {
if (mod & EMIT_32BIT_REG) {
if (get_mode_size_bits(mode) == 32)
break;
be_emit_char(mode_is_signed(mode) ? 's' : 'z');
......@@ -636,10 +636,10 @@ emit_R:
name = get_register_name_8bit_low(reg);
} else if (mod & EMIT_16BIT_REG) {
name = get_register_name_16bit(reg);
} else if (mod & EMIT_32BIT_REG) {
name = reg->name;
} else {
name = mod & EMIT_RESPECT_LS
? get_register_name_mode(reg, get_ia32_ls_mode(node))
: reg->name;
name = get_register_name_mode(reg, get_ia32_ls_mode(node));
}
be_emit_char('%');
be_emit_string(name);
......@@ -870,7 +870,7 @@ static void emit_ia32_Setcc(const ir_node *node)
ia32_emitf(node, "andb %>R, %<R", dreg, dreg);
}
} else {
ia32_emitf(node, "set%PX %#R", (int)cc, dreg);
ia32_emitf(node, "set%PX %R", (int)cc, dreg);
}
}
......@@ -1062,9 +1062,9 @@ static void emit_be_IncSP(const ir_node *node)
return;
if (offs > 0) {
ia32_emitf(node, "subl $%u, %D0", offs);
ia32_emitf(node, "subl $%u, %#D0", offs);
} else {
ia32_emitf(node, "addl $%u, %D0", -offs);
ia32_emitf(node, "addl $%u, %#D0", -offs);
}
}
......@@ -1082,7 +1082,7 @@ static void Copy_emitter(const ir_node *node, const ir_node *op)
if (in->cls == &ia32_reg_classes[CLASS_ia32_fp])
return;
ia32_emitf(node, "movl %R, %R", in, out);
ia32_emitf(node, "movl %#R, %#R", in, out);
}
static void emit_be_Copy(const ir_node *node)
......@@ -1107,11 +1107,11 @@ static void emit_be_Perm(const ir_node *node)
assert(cls == reg1->cls && "Register class mismatch at Perm");
if (cls == &ia32_reg_classes[CLASS_ia32_gp]) {
ia32_emitf(node, "xchg %R, %R", reg1, reg0);
ia32_emitf(node, "xchg %#R, %#R", reg1, reg0);
} else if (cls == &ia32_reg_classes[CLASS_ia32_xmm]) {
ia32_emitf(NULL, "xorpd %R, %R", reg1, reg0);
ia32_emitf(NULL, "xorpd %R, %R", reg0, reg1);
ia32_emitf(node, "xorpd %R, %R", reg1, reg0);
ia32_emitf(NULL, "xorpd %#R, %#R", reg1, reg0);
ia32_emitf(NULL, "xorpd %#R, %#R", reg0, reg1);
ia32_emitf(node, "xorpd %#R, %#R", reg1, reg0);
} else if (cls == &ia32_reg_classes[CLASS_ia32_fp]) {
/* is a NOP */
} else {
......@@ -1966,9 +1966,9 @@ static void bemit_perm(const ir_node *node)
bemit_xchg(reg0, reg1);
} else if (cls == &ia32_reg_classes[CLASS_ia32_xmm]) {
panic("unimplemented"); // TODO implement
//ia32_emitf(NULL, "xorpd %R, %R", reg1, reg0);
//ia32_emitf(NULL, "xorpd %R, %R", reg0, reg1);
//ia32_emitf(node, "xorpd %R, %R", reg1, reg0);
//ia32_emitf(NULL, "xorpd %#R, %#R", reg1, reg0);
//ia32_emitf(NULL, "xorpd %#R, %#R", reg0, reg1);
//ia32_emitf(node, "xorpd %#R, %#R", reg1, reg0);
} else if (cls == &ia32_reg_classes[CLASS_ia32_fp]) {
/* is a NOP */
} else {
......@@ -3196,7 +3196,7 @@ void ia32_emit_thunks(void)
be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
NULL);
ia32_emitf(NULL, "movl (%%esp), %R", reg);
ia32_emitf(NULL, "movl (%%esp), %#R", reg);
ia32_emitf(NULL, "ret");
be_gas_emit_function_epilog(entity);
}
......
......@@ -390,7 +390,7 @@ Add => {
AddMem => {
template => $binop_mem,
emit => "add%M %#S3, %AM",
emit => "add%M %S3, %AM",
latency => 1,
},
......@@ -442,7 +442,7 @@ IMul => {
IMulImm => {
template => $binop_commutative,
out_reqs => [ "gp", "flags", "mem" ],
emit => "imul%M %#S4, %#AS3, %#D0",
emit => "imul%M %S4, %AS3, %D0",
latency => 5,
},
......@@ -467,7 +467,7 @@ And => {
AndMem => {
template => $binop_mem,
emit => "and%M %#S3, %AM",
emit => "and%M %S3, %AM",
latency => 1,
},
......@@ -479,7 +479,7 @@ Or => {
OrMem => {
template => $binop_mem,
emit => "or%M %#S3, %AM",
emit => "or%M %S3, %AM",
latency => 1,
},
......@@ -501,7 +501,7 @@ Xor0 => {
XorMem => {
template => $binop_mem,
emit => "xor%M %#S3, %AM",
emit => "xor%M %S3, %AM",
latency => 1,
},
......@@ -520,7 +520,7 @@ Sub => {
SubMem => {
template => $binop_mem,
emit => "sub%M %#S3, %AM",
emit => "sub%M %S3, %AM",
latency => 1,
},
......@@ -636,7 +636,7 @@ RorMem => {
Rol => {
template => $shiftop,
emit => "rol%M %<,S1 %#D0",
emit => "rol%M %<,S1 %D0",
latency => 1,
},
......@@ -797,7 +797,7 @@ CMovcc => {
am => "source,binary",
attr_type => "ia32_condcode_attr_t",
attr => "x86_condition_code_t condition_code",
emit => "cmov%P5 %#AS4, %#D0",
emit => "cmov%P5 %AS4, %D0",
latency => 1,
mode => "first",
},
......@@ -945,7 +945,7 @@ Load => {
ins => [ "base", "index", "mem" ],
outs => [ "res", "unused", "M", "X_regular", "X_except" ],
latency => 0,
emit => "mov%#Ml %AM, %D0",
emit => "mov%#Ml %AM, %#D0",
},
Store => {
......@@ -958,7 +958,7 @@ Store => {
out_reqs => [ "mem", "exec", "exec" ],
ins => [ "base", "index", "mem", "val" ],
outs => [ "M", "X_regular", "X_except" ],
emit => "mov%M %#S3, %AM",
emit => "mov%M %S3, %AM",
latency => 2,
},
......@@ -1173,7 +1173,7 @@ CmpXChgMem => {
out_reqs => [ "eax", "flags", "mem" ],
ins => [ "base", "index", "mem", "old", "new" ],
outs => [ "res", "flags", "M" ],
emit => "lock cmpxchg%M %#S4, %AM",
emit => "lock cmpxchg%M %S4, %AM",
latency => 2,
},
......@@ -1193,7 +1193,7 @@ Xor0Low => {
out_reqs => [ "in_r0" ],
ins => [ "src" ],
outs => [ "res" ],
emit => "xor%M %#D0, %#D0",
emit => "xor%M %D0, %D0",
latency => 1,
},
......@@ -1216,7 +1216,7 @@ Outport => {
in_reqs => [ "edx", "eax", "mem" ],
out_reqs => [ "mem" ],
ins => [ "port", "value", "mem" ],
emit => "out%M %#S1, %^S0",
emit => "out%M %S1, %^S0",
latency => 1,
},
......@@ -1227,7 +1227,7 @@ Inport => {
out_reqs => [ "eax", "mem" ],
ins => [ "port", "mem" ],
outs => [ "res", "M" ],
emit => "in%M %^S0, %#D0",
emit => "in%M %^S0, %D0",
latency => 1,
},
......@@ -1298,21 +1298,21 @@ xAllOnes => {
# integer shift left, dword
xPslld => {
template => $xshiftop,
emit => "pslld %#S1, %D0",
emit => "pslld %S1, %D0",
latency => 3,
},
# integer shift left, qword
xPsllq => {
template => $xshiftop,
emit => "psllq %#S1, %D0",
emit => "psllq %S1, %D0",
latency => 3,
},
# integer shift right, dword
xPsrld => {
template => $xshiftop,
emit => "psrld %#S1, %D0",
emit => "psrld %S1, %D0",
latency => 1,
},
......@@ -1499,7 +1499,7 @@ Conv_I2I => {
out_reqs => [ "gp", "none", "mem", "exec", "exec" ],
ins => [ "base", "index", "mem", "val" ],
outs => [ "res", "unused", "M", "X_regular", "X_except" ],
emit => "mov%#Ml %#AS3, %D0",
emit => "mov%#Ml %AS3, %#D0",
am => "source,unary",
latency => 1,
attr => "ir_mode *smaller_mode",
......
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