Commit ec083e92 authored by Christoph Mallon's avatar Christoph Mallon
Browse files

Panic when asked to simulate a vfprem.

Simulating it as normal binop does only work in one special case.
It lacks the reverse form and selecting the second operand register.
So in many cases invalid code was generated silently.
parent 7005c8a4
......@@ -2349,16 +2349,6 @@ fprem => {
constructors => {},
},
# this node is just here, to keep the simulator running
# we can omit this when a fprem simulation function exists
fpremp => {
emit => 'fprem1\n'.
'fstp %F0',
latency => 20,
attr_type => "ia32_x87_attr_t",
constructors => {},
},
fdiv => {
state => "exc_pinned",
emit => 'fdiv%FM %AF',
......
......@@ -1118,7 +1118,6 @@ GEN_BINOP(fadd)
GEN_BINOPR(fsub)
GEN_BINOP(fmul)
GEN_BINOPR(fdiv)
GEN_BINOP(fprem)
GEN_UNOP(fabs)
GEN_UNOP(fchs)
......@@ -1131,6 +1130,14 @@ GEN_LOAD(fld1)
GEN_STORE(fst)
GEN_STORE(fist)
static int sim_fprem(x87_state *const state, ir_node *const n)
{
(void)state;
(void)n;
panic("TODO implement");
return NO_NODE_ADDED;
}
/**
* Simulate a virtual fisttp.
*
......
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