Commit ed9d4b91 authored by Christoph Mallon's avatar Christoph Mallon
Browse files

cleanup: Correct indentation.

parent a679562e
......@@ -576,7 +576,7 @@ static bool match_immediate_32(x86_imm32_t *imm, const ir_node *op,
* this is not what we want. */
if (!upper32_dont_care && val < 0
&& !mode_is_signed(get_tarval_mode(tv)))
return false;
return false;
} else {
val = 0;
}
......@@ -1442,7 +1442,7 @@ static ir_node *gen_Member(ir_node *const node)
panic("Sel not lowered");
if (is_parameter_entity(entity) &&
get_entity_parameter_number(entity) == IR_VA_START_PARAMETER_NUMBER)
panic("gen_Member: Request for invalid parameter (va_start parameter)");
panic("gen_Member: Request for invalid parameter (va_start parameter)");
amd64_addr_t addr = {
.immediate = {
......
......@@ -20,8 +20,7 @@ typedef struct reg_or_stackslot_t
{
const arch_register_t *reg0; /**< if != NULL, the first register used for this parameter. */
const arch_register_t *reg1; /**< if != NULL, the second register used. */
ir_type *type; /**< indicates that an entity of the specific
type is needed */
ir_type *type; /**< indicates that an entity of the specific type is needed */
unsigned offset; /**< if transmitted via stack, the offset for this parameter. */
ir_entity *entity; /**< entity in frame type */
} reg_or_stackslot_t;
......
......@@ -172,8 +172,8 @@ struct arch_register_t {
const arch_register_req_t *single_req;
unsigned short index; /**< The index of the register in
the class. */
unsigned short global_index; /**< The global index this
register in the architecture. */
/** The global index this register in the architecture. */
unsigned short global_index;
/** register number in dwarf debugging format */
unsigned short dwarf_number;
/** register number in instruction encoding */
......
......@@ -688,9 +688,9 @@ static void emit_compound_type(const ir_type *type)
int offset = get_entity_offset(member);
if (get_entity_bitfield_size(member) > 0) {
unsigned bit_offset = get_entity_bitfield_offset(member);
unsigned bit_size = get_entity_bitfield_size(member);
unsigned base_size = get_type_size_bytes(member_type);
unsigned bit_offset = get_entity_bitfield_offset(member);
unsigned bit_size = get_entity_bitfield_size(member);
unsigned base_size = get_type_size_bytes(member_type);
bit_offset = base_size*8 - bit_offset - bit_size;
......
......@@ -218,7 +218,7 @@ void x86_create_address_mode(x86_address_t *addr, ir_node *node,
assert(!addr->ip_base);
if (!(flags & x86_create_am_force) && x86_is_non_address_mode_node(node)
&& (!(flags & x86_create_am_double_use) || get_irn_n_edges(node) > 2)) {
addr->variant = X86_ADDR_BASE;
addr->variant = X86_ADDR_BASE;
addr->base = node;
return;
}
......@@ -332,8 +332,8 @@ tryit:
assert(addr->index == NULL && addr->scale == 0);
/* esp must be used as base */
if (is_Proj(right) && is_Start(get_Proj_pred(right))) {
addr->index = base;
addr->base = right;
addr->index = base;
addr->base = right;
} else {
addr->index = right;
}
......
......@@ -165,7 +165,7 @@ ir_node *x86_match_ASM(ir_node const *const node, x86_clobber_name_t const *cons
char const imm_type = parsed_constraint.immediate_type;
if (imm_type != '\0'
&& x86_match_immediate(&op->u.imm32, pred, imm_type)) {
op->kind = ASM_OP_IMMEDIATE;
op->kind = ASM_OP_IMMEDIATE;
continue;
}
......
......@@ -258,8 +258,8 @@ static bool sparc_rewrite_Conv(ir_node *node)
if (mode_is_float(from_mode) && mode_is_int(to_mode)
&& get_mode_size_bits(to_mode) <= 32
&& !mode_is_signed(to_mode)) {
rewrite_float_unsigned_Conv(node);
return true;
rewrite_float_unsigned_Conv(node);
return true;
}
return false;
......
......@@ -27,8 +27,8 @@ typedef struct reg_or_stackslot_t
for the 2nd part of the parameter */
const arch_register_t *reg0;
const arch_register_t *reg1;
ir_type *type; /**< indicates that an entity of the specific
type is needed */
/** indicates that an entity of the specific type is needed */
ir_type *type;
unsigned offset; /**< if transmitted via stack, the offset for
this parameter. */
ir_entity *entity; /**< entity in frame type */
......
......@@ -840,7 +840,7 @@ static void emit_sparc_Cas(const ir_node *node)
* which isn't guaranteed to be fulfilled in current firm backend */
if (arch_get_irn_register_out(node, pn_sparc_Cas_res) !=
arch_get_irn_register_in(node, n_sparc_Cas_new)) {
panic("sparc: should_be_same in Cas not fulfilled");
panic("sparc: should_be_same in Cas not fulfilled");
}
/* except for some patched gaisler binutils nobody understands cas
* in v8/leon mode, so we encode the cas in binary form */
......
......@@ -2019,7 +2019,7 @@ static ir_node *gen_compare_swap(ir_node *node)
assert(get_irn_mode(new) == mode);
if ((!mode_is_int(mode) && !mode_is_reference(mode))
|| get_mode_size_bits(mode) != 32) {
panic("sparc: compare and swap only allowed for 32bit values");
panic("sparc: compare and swap only allowed for 32bit values");
}
return cas;
......
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