Commit eda2347d authored by Christoph Mallon's avatar Christoph Mallon
Browse files

be: Use out registers instead of in register, when possible.

It is more consistent to use them and they are slightly faster to fetch.
parent 5e6af0de
......@@ -339,15 +339,13 @@ static void emit_be_Copy(const ir_node *irn)
static void emit_be_Perm(const ir_node *node)
{
const arch_register_t *in0, *in1;
arch_register_t const *const reg0 = arch_get_irn_register_out(node, 0);
arch_register_t const *const reg1 = arch_get_irn_register_out(node, 1);
in0 = arch_get_irn_register(get_irn_n(node, 0));
in1 = arch_get_irn_register(get_irn_n(node, 1));
arch_register_class_t const* const cls0 = reg0->reg_class;
assert(cls0 == reg1->reg_class && "Register class mismatch at Perm");
arch_register_class_t const* const cls0 = in0->reg_class;
assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
amd64_emitf(node, "xchg %R, %R", in0, in1);
amd64_emitf(node, "xchg %R, %R", reg0, reg1);
if (cls0 != &amd64_reg_classes[CLASS_amd64_gp]) {
panic("unexpected register class in be_Perm (%+F)", node);
......
......@@ -618,9 +618,9 @@ static void emit_be_Copy(const ir_node *irn)
static void emit_be_Perm(const ir_node *irn)
{
arm_emitf(irn,
"eor %S0, %S0, %S1\n"
"eor %S1, %S0, %S1\n"
"eor %S0, %S0, %S1");
"eor %D0, %D0, %D1\n"
"eor %D1, %D0, %D1\n"
"eor %D0, %D0, %D1");
}
static void emit_be_MemPerm(const ir_node *node)
......
......@@ -1203,20 +1203,18 @@ static void emit_be_CopyKeep(const ir_node *node)
*/
static void emit_be_Perm(const ir_node *node)
{
const arch_register_t *in0, *in1;
arch_register_t const *const reg0 = arch_get_irn_register_out(node, 0);
arch_register_t const *const reg1 = arch_get_irn_register_out(node, 1);
in0 = arch_get_irn_register(get_irn_n(node, 0));
in1 = arch_get_irn_register(get_irn_n(node, 1));
arch_register_class_t const *const cls0 = in0->reg_class;
assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
arch_register_class_t const *const cls0 = reg0->reg_class;
assert(cls0 == reg1->reg_class && "Register class mismatch at Perm");
if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
ia32_emitf(node, "xchg %R, %R", in1, in0);
ia32_emitf(node, "xchg %R, %R", reg1, reg0);
} else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
ia32_emitf(node, "xorpd %R, %R", in1, in0);
ia32_emitf(NULL, "xorpd %R, %R", reg1, reg0);
ia32_emitf(NULL, "xorpd %R, %R", reg0, reg1);
ia32_emitf(node, "xorpd %R, %R", reg1, reg0);
} else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
/* is a NOP */
} else {
......@@ -2076,26 +2074,26 @@ static void bemit_copy(const ir_node *copy)
static void bemit_perm(const ir_node *node)
{
const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
const arch_register_class_t *cls0 = in0->reg_class;
arch_register_t const *const reg0 = arch_get_irn_register_out(node, 0);
arch_register_t const *const reg1 = arch_get_irn_register_out(node, 1);
arch_register_class_t const *const cls0 = reg0->reg_class;
assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
assert(cls0 == reg1->reg_class && "Register class mismatch at Perm");
if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
if (in0->index == REG_GP_EAX) {
bemit8(0x90 + reg_gp_map[in1->index]);
} else if (in1->index == REG_GP_EAX) {
bemit8(0x90 + reg_gp_map[in0->index]);
if (reg0->index == REG_GP_EAX) {
bemit8(0x90 + reg_gp_map[reg1->index]);
} else if (reg1->index == REG_GP_EAX) {
bemit8(0x90 + reg_gp_map[reg0->index]);
} else {
bemit8(0x87);
bemit_modrr(in0, in1);
bemit_modrr(reg0, reg1);
}
} else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
panic("unimplemented"); // TODO implement
//ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
//ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
//ia32_emitf(node, "xorpd %R, %R", in1, in0);
//ia32_emitf(NULL, "xorpd %R, %R", reg1, reg0);
//ia32_emitf(NULL, "xorpd %R, %R", reg0, reg1);
//ia32_emitf(node, "xorpd %R, %R", reg1, reg0);
} else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
/* is a NOP */
} else {
......
......@@ -485,7 +485,7 @@ Shl => {
out => [ "in_r1 !in_r2", "flags" ] },
ins => [ "val", "count" ],
outs => [ "res", "flags" ],
emit => 'shl%M %<S1, %S0',
emit => 'shl%M %<S1, %D0',
latency => 1,
mode => $mode_gp,
modified_flags => $status_flags
......@@ -520,7 +520,7 @@ Shr => {
out => [ "in_r1 !in_r2", "flags" ] },
ins => [ "val", "count" ],
outs => [ "res", "flags" ],
emit => 'shr%M %<S1, %S0',
emit => 'shr%M %<S1, %D0',
mode => $mode_gp,
latency => 1,
modified_flags => $status_flags
......@@ -555,7 +555,7 @@ Sar => {
out => [ "in_r1 !in_r2", "flags" ] },
ins => [ "val", "count" ],
outs => [ "res", "flags" ],
emit => 'sar%M %<S1, %S0',
emit => 'sar%M %<S1, %D0',
latency => 1,
mode => $mode_gp,
modified_flags => $status_flags
......@@ -578,7 +578,7 @@ Ror => {
out => [ "in_r1 !in_r2", "flags" ] },
ins => [ "val", "count" ],
outs => [ "res", "flags" ],
emit => 'ror%M %<S1, %S0',
emit => 'ror%M %<S1, %D0',
latency => 1,
mode => $mode_gp,
modified_flags => $status_flags
......@@ -622,7 +622,7 @@ Neg => {
irn_flags => [ "rematerializable" ],
reg_req => { in => [ "gp" ],
out => [ "in_r1", "flags" ] },
emit => 'neg%M %S0',
emit => 'neg%M %D0',
ins => [ "val" ],
outs => [ "res", "flags" ],
latency => 1,
......@@ -656,7 +656,7 @@ Inc => {
out => [ "in_r1", "flags" ] },
ins => [ "val" ],
outs => [ "res", "flags" ],
emit => 'inc%M %S0',
emit => 'inc%M %D0',
mode => $mode_gp,
latency => 1,
modified_flags => $status_flags_wo_cf
......@@ -679,7 +679,7 @@ Dec => {
out => [ "in_r1", "flags" ] },
ins => [ "val" ],
outs => [ "res", "flags" ],
emit => 'dec%M %S0',
emit => 'dec%M %D0',
mode => $mode_gp,
latency => 1,
modified_flags => $status_flags_wo_cf
......@@ -702,7 +702,7 @@ Not => {
out => [ "in_r1" ] },
ins => [ "val" ],
outs => [ "res" ],
emit => 'not%M %S0',
emit => 'not%M %D0',
latency => 1,
mode => $mode_gp,
# no flags modified
......@@ -755,7 +755,7 @@ XorHighLow => {
state => "exc_pinned",
reg_req => { in => [ "eax ebx ecx edx" ],
out => [ "in_r1", "flags" ] },
emit => 'xorb %>S0, %<S0',
emit => 'xorb %>D0, %<D0',
ins => [ "value" ],
outs => [ "res", "flags" ],
latency => 1,
......@@ -1232,7 +1232,7 @@ Bswap => {
reg_req => { in => [ "gp" ],
out => [ "in_r1" ] },
outs => [ "res" ],
emit => 'bswap%M %S0',
emit => 'bswap%M %D0',
ins => [ "val" ],
latency => 1,
mode => $mode_gp,
......@@ -1245,7 +1245,7 @@ Bswap16 => {
irn_flags => [ "rematerializable" ],
reg_req => { in => [ "eax ebx ecx edx" ],
out => [ "in_r1" ] },
emit => 'xchg %<S0, %>S0',
emit => 'xchg %<D0, %>D0',
ins => [ "val" ],
latency => 1,
mode => $mode_gp,
......
......@@ -782,11 +782,11 @@ static void emit_be_Perm(const ir_node *irn)
{
ir_mode *mode = get_irn_mode(get_irn_n(irn, 0));
if (mode_is_float(mode)) {
const arch_register_t *reg0 = arch_get_irn_register_in(irn, 0);
const arch_register_t *reg1 = arch_get_irn_register_in(irn, 1);
arch_register_t const *const reg0 = arch_get_irn_register_out(irn, 0);
arch_register_t const *const reg1 = arch_get_irn_register_out(irn, 1);
unsigned reg_idx0 = reg0->global_index;
unsigned reg_idx1 = reg1->global_index;
unsigned width = arch_get_irn_register_req_in(irn, 0)->width;
unsigned width = arch_get_irn_register_req_out(irn, 0)->width;
for (unsigned i = 0; i < width; ++i) {
const arch_register_t *r0 = &sparc_registers[reg_idx0+i];
const arch_register_t *r1 = &sparc_registers[reg_idx1+i];
......@@ -795,9 +795,9 @@ static void emit_be_Perm(const ir_node *irn)
sparc_emitf(irn, "fmovs %%f31, %R", r1);
}
} else {
sparc_emitf(irn, "xor %S1, %S0, %S0");
sparc_emitf(irn, "xor %S1, %S0, %S1");
sparc_emitf(irn, "xor %S1, %S0, %S0");
sparc_emitf(irn, "xor %D1, %D0, %D0");
sparc_emitf(irn, "xor %D1, %D0, %D1");
sparc_emitf(irn, "xor %D1, %D0, %D0");
}
}
......
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