Commit f2eb5e7f authored by Andreas Fried's avatar Andreas Fried
Browse files

amd64: Add instruction setcc.

parent a3b3ab86
......@@ -503,8 +503,15 @@ end_of_mods:
case 'P': {
x86_condition_code_t cc;
if (*fmt == 'X') {
// Fetch cc from varargs
++fmt;
cc = (x86_condition_code_t)va_arg(ap, int);
} else if (is_digit(*fmt)) {
// Format string is backwards compatible to IA32 backend.
// Fetch cc from node attributes
++fmt;
assert(amd64_has_cc_attr(node));
cc = get_amd64_cc_attr_const(node)->cc;
} else {
panic("unknown modifier");
}
......
......@@ -138,10 +138,13 @@ static void init_amd64_switch_attributes(ir_node *node,
}
}
static void init_amd64_cc_attributes(ir_node *node, x86_condition_code_t cc)
static void init_amd64_cc_attributes(ir_node *node,
x86_condition_code_t cc,
amd64_insn_mode_t insn_mode)
{
amd64_cc_attr_t *attr = get_amd64_cc_attr(node);
attr->cc = cc;
attr->cc = cc;
attr->insn_mode = insn_mode;
}
static void init_amd64_movimm_attributes(ir_node *node,
......
......@@ -103,16 +103,21 @@ static inline amd64_switch_jmp_attr_t *get_amd64_switch_jmp_attr(ir_node *node)
return (amd64_switch_jmp_attr_t*)get_irn_generic_attr(node);
}
static inline bool amd64_has_cc_attr(const ir_node *node)
{
return is_amd64_jcc(node) || is_amd64_setcc(node);
}
static inline const amd64_cc_attr_t *get_amd64_cc_attr_const(
const ir_node *node)
{
assert(is_amd64_jcc(node));
assert(amd64_has_cc_attr(node));
return (const amd64_cc_attr_t*)get_irn_generic_attr_const(node);
}
static inline amd64_cc_attr_t *get_amd64_cc_attr(ir_node *node)
{
assert(is_amd64_jcc(node));
assert(amd64_has_cc_attr(node));
return (amd64_cc_attr_t*)get_irn_generic_attr(node);
}
......
......@@ -110,6 +110,7 @@ typedef struct {
typedef struct {
amd64_attr_t base;
x86_condition_code_t cc;
ENUMBF(amd64_insn_mode_t) insn_mode : 3;
} amd64_cc_attr_t;
typedef struct {
......
......@@ -68,7 +68,7 @@ $mode_xmm = "amd64_mode_xmm";
."\tinit_amd64_switch_attributes(res, table, table_entity);",
amd64_cc_attr_t =>
"init_amd64_attributes(res, irn_flags, in_reqs, n_res, AMD64_OP_NONE);\n"
."\tinit_amd64_cc_attributes(res, cc);",
."\tinit_amd64_cc_attributes(res, cc, insn_mode);",
amd64_movimm_attr_t =>
"init_amd64_attributes(res, irn_flags, in_reqs, n_res, AMD64_OP_IMM64);\n"
."\tinit_amd64_movimm_attributes(res, insn_mode, imm);",
......@@ -399,6 +399,19 @@ cmp => {
emit => "cmp%M %AM",
},
# TODO Setcc can also operate on memory
setcc => {
irn_flags => [ ],
in_reqs => [ "eflags" ],
out_reqs => [ "gp" ],
ins => [ "eflags" ],
outs => [ "res" ],
attr_type => "amd64_cc_attr_t",
attr => "x86_condition_code_t cc",
fixed => "amd64_insn_mode_t insn_mode = INSN_MODE_8;",
emit => "set%P0 %D0",
},
lea => {
irn_flags => [ "rematerializable" ],
in_reqs => "...",
......@@ -419,6 +432,7 @@ jcc => {
outs => [ "false", "true" ],
attr_type => "amd64_cc_attr_t",
attr => "x86_condition_code_t cc",
fixed => "amd64_insn_mode_t insn_mode = INSN_MODE_64;",
},
mov_store => {
......
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