Commit f8459487 authored by Christoph Mallon's avatar Christoph Mallon
Browse files

Remove the very thin wrapper function arch_register_get_index().

parent 96cdb5f8
......@@ -251,7 +251,7 @@ bool arch_reg_is_allocatable(const arch_register_req_t *req,
if (req->type & arch_register_req_type_limited) {
if (arch_register_get_class(reg) != req->cls)
return false;
return rbitset_is_set(req->limited, arch_register_get_index(reg));
return rbitset_is_set(req->limited, reg->index);
}
return req->cls == arch_register_get_class(reg);
}
......
......@@ -245,11 +245,6 @@ static inline const arch_register_class_t *arch_register_get_class(
return reg->reg_class;
}
static inline unsigned arch_register_get_index(const arch_register_t *reg)
{
return reg->index;
}
/**
* A class of registers.
* Like general purpose or floating point.
......
......@@ -423,14 +423,12 @@ static void assign(ir_node *block, void *env_ptr)
be_lv_foreach(lv, block, be_lv_state_in, irn) {
if (has_reg_class(env, irn)) {
const arch_register_t *reg = arch_get_irn_register(irn);
int col;
assert(reg && "Node must have been assigned a register");
col = arch_register_get_index(reg);
DBG((dbg, LEVEL_4, "%+F has reg %s\n", irn, reg->name));
/* Mark the color of the live in value as used. */
int const col = reg->index;
bitset_set(colors, col);
bitset_set(in_colors, col);
......@@ -477,13 +475,10 @@ static void assign(ir_node *block, void *env_ptr)
} else if (!b->is_def) {
/* Clear the color upon a use. */
const arch_register_t *reg = arch_get_irn_register(irn);
int col;
assert(reg && "Register must have been assigned");
col = arch_register_get_index(reg);
bitset_clear(colors, col);
bitset_clear(colors, reg->index);
bitset_clear(live, nr);
}
}
......
......@@ -215,7 +215,7 @@ static void block_dims_walker(ir_node *block, void *data)
list_for_each_entry_reverse(border_t, b, head, list) {
ir_node *irn = b->irn;
const arch_register_t *reg = arch_get_irn_register(irn);
int col = arch_register_get_index(reg);
int col = reg->index;
dims->max_step = MAX(dims->max_step, b->step);
dims->max_color = MAX(dims->max_color, col);
......@@ -335,9 +335,8 @@ static void draw_block(ir_node *bl, void *data)
list_for_each_entry(border_t, b, head, list) {
if (b->is_def) {
const arch_register_t *reg = arch_get_irn_register(b->irn);
int col = arch_register_get_index(reg);
int live_out = be_is_live_out(lv, bl, b->irn);
int x = (col + 1) * opts->h_inter_gap;
int x = (reg->index + 1) * opts->h_inter_gap;
int ystart = (b->step) * opts->v_inter_gap;
int ystop = (b->other_end->step) * opts->v_inter_gap + (live_out ? 0 : opts->v_inter_gap / 2);
......@@ -362,9 +361,8 @@ static void draw_block(ir_node *bl, void *data)
be_lv_foreach(lv, bl, be_lv_state_in, irn) {
if (arch_irn_consider_in_reg_alloc(env->cls, irn)) {
const arch_register_t *reg = arch_get_irn_register(irn);
int col = arch_register_get_index(reg);
int x = (col + 1) * opts->h_inter_gap;
color_t color;
int x = (reg->index + 1) * opts->h_inter_gap;
color_t color;
reg_to_color(env, bl, irn, &color);
......
......@@ -160,7 +160,7 @@ static co_mst_irn_t *co_mst_irn_init(co_mst_env_t *env, const ir_node *irn)
res->tmp_col = -1;
res->int_neighs = NULL;
res->int_aff_neigh = 0;
res->col = arch_register_get_index(arch_get_irn_register(irn));
res->col = arch_get_irn_register(irn)->index;
res->init_col = res->col;
INIT_LIST_HEAD(&res->list);
......
......@@ -59,7 +59,7 @@ struct copy_opt_t {
static inline unsigned get_irn_col(const ir_node *node)
{
return arch_register_get_index(arch_get_irn_register(node));
return arch_get_irn_register(node)->index;
}
static inline void set_irn_col(const arch_register_class_t *cls, ir_node *node,
......
......@@ -834,7 +834,7 @@ const arch_register_req_t *be_create_reg_req(struct obstack *obst,
unsigned *limited_bitset;
limited_bitset = rbitset_obstack_alloc(obst, arch_register_class_n_regs(cls));
rbitset_set(limited_bitset, arch_register_get_index(reg));
rbitset_set(limited_bitset, reg->index);
req->type = arch_register_req_type_limited | additional_types;
req->cls = cls;
......
......@@ -538,7 +538,7 @@ static void combine_congruence_classes(void)
*/
static void use_reg(ir_node *node, const arch_register_t *reg, unsigned width)
{
unsigned r = arch_register_get_index(reg);
unsigned r = reg->index;
for (unsigned r0 = r; r0 < r + width; ++r0)
assignments[r0] = node;
arch_set_irn_register(node, reg);
......@@ -551,7 +551,7 @@ static void free_reg_of_value(ir_node *node)
const arch_register_t *reg = arch_get_irn_register(node);
const arch_register_req_t *req = arch_get_irn_register_req(node);
unsigned r = arch_register_get_index(reg);
unsigned r = reg->index;
/* assignment->value may be NULL if a value is used at 2 inputs
* so it gets freed twice. */
for (unsigned r0 = r; r0 < r + req->width; ++r0) {
......@@ -603,7 +603,7 @@ static bool try_optimistic_split(ir_node *to_split, ir_node *before,
return false;
const arch_register_t *from_reg = arch_get_irn_register(to_split);
unsigned from_r = arch_register_get_index(from_reg);
unsigned from_r = from_reg->index;
ir_node *block = get_nodes_block(before);
float split_threshold = (float)get_block_execfreq(block) * SPLIT_DELTA;
......@@ -670,7 +670,7 @@ static bool try_optimistic_split(ir_node *to_split, ir_node *before,
unsigned width = 1;
mark_as_copy_of(copy, to_split);
/* hacky, but correct here */
if (assignments[arch_register_get_index(from_reg)] == to_split)
if (assignments[from_reg->index] == to_split)
free_reg_of_value(to_split);
use_reg(copy, reg, width);
sched_add_before(before, copy);
......@@ -715,7 +715,7 @@ static void assign_reg(const ir_node *block, ir_node *node,
ir_node *in = get_irn_n(in_node, i);
const arch_register_t *reg = arch_get_irn_register(in);
unsigned reg_index = arch_register_get_index(reg);
unsigned reg_index = reg->index;
/* if the value didn't die here then we should not propagate the
* should_be_same info */
......@@ -871,7 +871,7 @@ static void permute_values(ir_nodeset_t *live_nodes, ir_node *before,
}
/* old register has 1 user less, permutation is resolved */
assert(arch_register_get_index(arch_get_irn_register(src)) == old_r);
assert(arch_get_irn_register(src)->index == old_r);
permutation[r] = r;
assert(n_used[old_r] > 0);
......@@ -1022,7 +1022,7 @@ static void determine_live_through_regs(unsigned *bitset, ir_node *node)
ir_node *op = get_irn_n(node, i);
const arch_register_t *reg = arch_get_irn_register(op);
rbitset_clear(bitset, arch_register_get_index(reg));
rbitset_clear(bitset, reg->index);
}
}
......@@ -1049,7 +1049,7 @@ static void solve_lpp(ir_nodeset_t *live_nodes, ir_node *node,
const unsigned *limited = req->limited;
const arch_register_t *reg = arch_get_irn_register(op);
unsigned current_reg = arch_register_get_index(reg);
unsigned current_reg = reg->index;
for (unsigned r = 0; r < n_regs; ++r) {
if (rbitset_is_set(limited, r))
continue;
......@@ -1181,7 +1181,7 @@ static void enforce_constraints(ir_nodeset_t *live_nodes, ir_node *node,
if (req->width > 1)
double_width = true;
const arch_register_t *reg = arch_get_irn_register(op);
unsigned reg_index = arch_register_get_index(reg);
unsigned reg_index = reg->index;
if (req->type & arch_register_req_type_aligned) {
if (!is_aligned(reg_index, req->width)) {
good = false;
......@@ -1269,7 +1269,7 @@ static void enforce_constraints(ir_nodeset_t *live_nodes, ir_node *node,
const unsigned *limited = req->limited;
const arch_register_t *reg = arch_get_irn_register(op);
unsigned current_reg = arch_register_get_index(reg);
unsigned current_reg = reg->index;
for (unsigned r = 0; r < n_regs; ++r) {
if (rbitset_is_set(limited, r))
continue;
......@@ -1358,7 +1358,7 @@ static void add_phi_permutations(ir_node *block, int p)
assert(a >= 0);
const arch_register_t *reg = arch_get_irn_register(phi);
int regn = arch_register_get_index(reg);
int regn = reg->index;
/* same register? nothing to do */
if (regn == a)
continue;
......@@ -1392,7 +1392,7 @@ static void add_phi_permutations(ir_node *block, int p)
/* we have permuted all values into the correct registers so we can
simply query which value occupies the phis register in the
predecessor */
int a = arch_register_get_index(arch_get_irn_register(phi));
int a = arch_get_irn_register(phi)->index;
ir_node *op = pred_info->assignments[a];
set_Phi_pred(phi, p, op);
}
......@@ -1423,9 +1423,8 @@ static void adapt_phi_prefs(ir_node *phi)
continue;
/* give bonus for already assigned register */
float weight = (float)get_block_execfreq(pred_block);
unsigned r = arch_register_get_index(reg);
info->prefs[r] += weight * AFF_PHI;
float weight = (float)get_block_execfreq(pred_block);
info->prefs[reg->index] += weight * AFF_PHI;
}
}
......@@ -1690,7 +1689,7 @@ static void allocate_coalesce_block(ir_node *block, void *data)
continue;
const arch_register_t *reg = arch_get_irn_register(op);
rbitset_set(forbidden_regs, arch_register_get_index(reg));
rbitset_set(forbidden_regs, reg->index);
}
/* free registers of values last used at this instruction */
......
......@@ -317,7 +317,7 @@ void be_abi_fix_stack_nodes(ir_graph *irg)
new_sp_req->width = 1;
limited_bitset = rbitset_obstack_alloc(obst, new_sp_req->cls->n_regs);
rbitset_set(limited_bitset, arch_register_get_index(sp));
rbitset_set(limited_bitset, sp->index);
new_sp_req->limited = limited_bitset;
if (!rbitset_is_set(birg->allocatable_regs, sp->global_index)) {
......
......@@ -606,12 +606,12 @@ static vfp_liveness vfp_liveness_transfer(ir_node *irn, vfp_liveness live)
if (arch_irn_consider_in_reg_alloc(cls, proj)) {
const arch_register_t *reg = x87_get_irn_register(proj);
live &= ~(1 << arch_register_get_index(reg));
live &= ~(1 << reg->index);
}
}
} else if (arch_irn_consider_in_reg_alloc(cls, irn)) {
const arch_register_t *reg = x87_get_irn_register(irn);
live &= ~(1 << arch_register_get_index(reg));
live &= ~(1 << reg->index);
}
for (i = 0, n = get_irn_arity(irn); i < n; ++i) {
......@@ -620,7 +620,7 @@ static vfp_liveness vfp_liveness_transfer(ir_node *irn, vfp_liveness live)
if (mode_is_float(get_irn_mode(op)) &&
arch_irn_consider_in_reg_alloc(cls, op)) {
const arch_register_t *reg = x87_get_irn_register(op);
live |= 1 << arch_register_get_index(reg);
live |= 1 << reg->index;
}
}
return live;
......@@ -646,14 +646,14 @@ static vfp_liveness vfp_liveness_end_of_block(x87_simulator *sim, const ir_node
continue;
reg = x87_get_irn_register(node);
live |= 1 << arch_register_get_index(reg);
live |= 1 << reg->index;
}
return live;
}
/** get the register mask from an arch_register */
#define REGMASK(reg) (1 << (arch_register_get_index(reg)))
#define REGMASK(reg) (1 << (reg->index))
/**
* Return a bitset of argument registers which are live at the end of a node.
......@@ -749,8 +749,8 @@ static int sim_binop(x87_state *const state, ir_node *const n, ir_op *const op)
const arch_register_t *op1_reg = x87_get_irn_register(op1);
const arch_register_t *op2_reg = x87_get_irn_register(op2);
const arch_register_t *out = x87_irn_get_register(n, pn_ia32_res);
int reg_index_1 = arch_register_get_index(op1_reg);
int reg_index_2 = arch_register_get_index(op2_reg);
int reg_index_1 = op1_reg->index;
int reg_index_2 = op2_reg->index;
vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out));
int op1_live_after;
int op2_live_after;
......@@ -767,7 +767,7 @@ static int sim_binop(x87_state *const state, ir_node *const n, ir_op *const op)
attr = get_ia32_x87_attr(n);
permuted = attr->attr.data.ins_permuted;
int const out_reg_idx = arch_register_get_index(out);
int const out_reg_idx = out->index;
if (reg_index_2 != REG_VFP_VFP_NOREG) {
assert(!permuted);
......@@ -905,9 +905,9 @@ static int sim_unop(x87_state *state, ir_node *n, ir_op *op)
ir_node *const op1 = get_irn_n(n, 0);
arch_register_t const *const op1_reg = x87_get_irn_register(op1);
int const op1_reg_idx = arch_register_get_index(op1_reg);
int const op1_reg_idx = op1_reg->index;
int const op1_idx = x87_on_stack(state, op1_reg_idx);
int const out_reg_idx = arch_register_get_index(out);
int const out_reg_idx = out->index;
if (is_vfp_live(op1_reg_idx, live)) {
/* push the operand here */
x87_create_fpush(state, n, op1_idx, out_reg_idx, op1);
......@@ -941,7 +941,7 @@ static int sim_load(x87_state *state, ir_node *n, ir_op *op, int res_pos)
ia32_x87_attr_t *attr;
DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
x87_push(state, out->index, x87_patch_insn(n, op));
assert(out == x87_irn_get_register(n, res_pos));
attr = get_ia32_x87_attr(n);
attr->x87[2] = out = get_st_reg(0);
......@@ -983,7 +983,7 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op)
bool do_pop = false;
int insn = NO_NODE_ADDED;
int const op2_reg_idx = arch_register_get_index(op2);
int const op2_reg_idx = op2->index;
int const op2_idx = x87_on_stack(state, op2_reg_idx);
unsigned const live = vfp_live_args_after(state->sim, n, 0);
int const live_after_node = is_vfp_live(op2_reg_idx, live);
......@@ -1121,10 +1121,8 @@ static int sim_fisttp(x87_state *state, ir_node *n)
ir_node *val = get_irn_n(n, n_ia32_vfst_val);
const arch_register_t *op2 = x87_get_irn_register(val);
ia32_x87_attr_t *attr;
int op2_reg_idx, op2_idx;
op2_reg_idx = arch_register_get_index(op2);
op2_idx = x87_on_stack(state, op2_reg_idx);
int const op2_idx = x87_on_stack(state, op2->index);
DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, op2->name));
assert(op2_idx >= 0);
......@@ -1160,7 +1158,7 @@ static int sim_FtstFnstsw(x87_state *state, ir_node *n)
ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
ir_node *op1_node = get_irn_n(n, n_ia32_vFtstFnstsw_left);
const arch_register_t *reg1 = x87_get_irn_register(op1_node);
int reg_index_1 = arch_register_get_index(reg1);
int reg_index_1 = reg1->index;
int op1_idx = x87_on_stack(state, reg_index_1);
unsigned live = vfp_live_args_after(sim, n, 0);
......@@ -1208,8 +1206,8 @@ static int sim_Fucom(x87_state *state, ir_node *n)
ir_node *op2_node = get_irn_n(n, n_ia32_vFucomFnstsw_right);
const arch_register_t *op1 = x87_get_irn_register(op1_node);
const arch_register_t *op2 = x87_get_irn_register(op2_node);
int reg_index_1 = arch_register_get_index(op1);
int reg_index_2 = arch_register_get_index(op2);
int reg_index_1 = op1->index;
int reg_index_2 = op2->index;
unsigned live = vfp_live_args_after(sim, n, 0);
bool permuted = attr->attr.data.ins_permuted;
bool xchg = false;
......@@ -1452,7 +1450,7 @@ static int sim_Keep(x87_state *state, ir_node *node)
if (arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
continue;
reg_id = arch_register_get_index(op_reg);
reg_id = op_reg->index;
live = vfp_live_args_after(state->sim, node, 0);
op_stack_idx = x87_on_stack(state, reg_id);
......@@ -1532,16 +1530,16 @@ static ir_node *create_Copy(x87_state *state, ir_node *n)
/* copy a constant */
res = (*cnstr)(n_dbg, block, mode);
x87_push(state, arch_register_get_index(out), res);
x87_push(state, out->index, res);
attr = get_ia32_x87_attr(res);
attr->x87[2] = get_st_reg(0);
} else {
int op1_idx = x87_on_stack(state, arch_register_get_index(op1));
int op1_idx = x87_on_stack(state, op1->index);
res = new_bd_ia32_fpushCopy(n_dbg, block, pred, mode);
x87_push(state, arch_register_get_index(out), res);
x87_push(state, out->index, res);
attr = get_ia32_x87_attr(res);
attr->x87[0] = get_st_reg(op1_idx);
......@@ -1574,7 +1572,7 @@ static int sim_Copy(x87_state *state, ir_node *n)
DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n, op1->name, out->name));
DEBUG_ONLY(vfp_dump_live(live);)
if (is_vfp_live(arch_register_get_index(op1), live)) {
if (is_vfp_live(op1->index, live)) {
/* Operand is still live, a real copy. We need here an fpush that can
hold a a register, so use the fpushCopy or recreate constants */
ir_node *const node = create_Copy(state, n);
......@@ -1597,8 +1595,8 @@ static int sim_Copy(x87_state *state, ir_node *n)
DB((dbg, LEVEL_1, "<<< %+F %s -> ?\n", node, op1->name));
} else {
/* Just a virtual copy. */
int const op1_idx = x87_on_stack(state, arch_register_get_index(op1));
x87_set_st(state, arch_register_get_index(out), n, op1_idx);
int const op1_idx = x87_on_stack(state, op1->index);
x87_set_st(state, out->index, n, op1_idx);
}
return NO_NODE_ADDED;
}
......@@ -1666,7 +1664,7 @@ static int sim_Call(x87_state *state, ir_node *n)
if (mode && mode_is_float(mode)) {
ir_node *const resproj = get_call_result_proj(n);
arch_register_t const *const reg = x87_get_irn_register(resproj);
x87_push(state, arch_register_get_index(reg), resproj);
x87_push(state, reg->index, resproj);
}
}
DB((dbg, LEVEL_1, "Stack after: "));
......@@ -1732,7 +1730,7 @@ static int sim_Perm(x87_state *state, ir_node *irn)
/* collect old stack positions */
for (i = 0; i < n; ++i) {
const arch_register_t *inreg = x87_get_irn_register(get_irn_n(irn, i));
int idx = x87_on_stack(state, arch_register_get_index(inreg));
int idx = x87_on_stack(state, inreg->index);
assert(idx >= 0 && "Perm argument not on x87 stack");
......@@ -1745,7 +1743,7 @@ static int sim_Perm(x87_state *state, ir_node *irn)
long num = get_Proj_proj(proj);
assert(0 <= num && num < n && "More Proj's than Perm inputs");
x87_set_st(state, arch_register_get_index(out), proj, stack_pos[(unsigned)num]);
x87_set_st(state, out->index, proj, stack_pos[(unsigned)num]);
}
DB((dbg, LEVEL_1, "<<< %+F\n", irn));
......
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