Skip to content
GitLab
Projects
Groups
Snippets
/
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Sign in
Toggle navigation
Menu
Open sidebar
Zwinkau
libfirm
Commits
fc81b817
Commit
fc81b817
authored
Jun 15, 2011
by
Matthias Braun
Browse files
fix a bunch of warnings reported by cparser
parent
780ca0cd
Changes
15
Hide whitespace changes
Inline
Side-by-side
ir/be/ia32/bearch_ia32.c
View file @
fc81b817
...
...
@@ -94,9 +94,7 @@
transformer_t
be_transformer
=
TRANSFORMER_DEFAULT
;
#endif
DEBUG_ONLY
(
static
firm_dbg_module_t
*
dbg
=
NULL
;)
ir_mode
*
ia32_mode_fpcw
=
NULL
;
ir_mode
*
ia32_mode_fpcw
=
NULL
;
/** The current omit-fp state */
static
ir_type
*
omit_fp_between_type
=
NULL
;
...
...
@@ -118,7 +116,7 @@ static ia32_intrinsic_env_t intrinsic_env = {
};
typedef
ir_node
*
(
*
create_const_node_func
)
(
dbg_info
*
dbg
,
ir_node
*
block
);
typedef
ir_node
*
(
*
create_const_node_func
)
(
dbg_info
*
dbg
i
,
ir_node
*
block
);
/**
* Used to create per-graph unique pseudo nodes.
...
...
@@ -396,7 +394,7 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_
ir_mode *mode;
ir_mode *irn_mode;
ir_node *block, *noreg, *nomem;
dbg_info *dbg;
dbg_info *dbg
i
;
/* we cannot invert non-ia32 irns */
if (! is_ia32_irn(irn))
...
...
@@ -420,7 +418,7 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_
irn_mode = get_irn_mode(irn);
noreg = get_irn_n(irn, 0);
nomem = get_irg_no_mem(irg);
dbg
= get_irn_dbg_info(irn);
dbg
i
= get_irn_dbg_info(irn);
/* initialize structure */
inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
...
...
@@ -432,7 +430,7 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_
if (get_ia32_immop_type(irn) == ia32_ImmConst) {
/* we have an add with a const here */
/* invers == add with negated const */
inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->nodes[0] = new_bd_ia32_Add(dbg
i
, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
...
...
@@ -441,13 +439,13 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_
else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
/* we have an add with a symconst here */
/* invers == sub with const */
inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->nodes[0] = new_bd_ia32_Sub(dbg
i
, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += 2;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal add: inverse == sub */
inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
inverse->nodes[0] = new_bd_ia32_Sub(dbg
i
, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
inverse->costs += 2;
}
break;
...
...
@@ -455,17 +453,17 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_
if (get_ia32_immop_type(irn) != ia32_ImmNone) {
/* we have a sub with a const/symconst here */
/* invers == add with this const */
inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->nodes[0] = new_bd_ia32_Add(dbg
i
, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal sub */
if (i == n_ia32_binary_left) {
inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
inverse->nodes[0] = new_bd_ia32_Add(dbg
i
, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
}
else {
inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
inverse->nodes[0] = new_bd_ia32_Sub(dbg
i
, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
}
inverse->costs += 1;
}
...
...
@@ -473,23 +471,23 @@ static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_
case iro_ia32_Xor:
if (get_ia32_immop_type(irn) != ia32_ImmNone) {
/* xor with const: inverse = xor */
inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->nodes[0] = new_bd_ia32_Xor(dbg
i
, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
}
else {
/* normal xor */
inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
inverse->nodes[0] = new_bd_ia32_Xor(dbg
i
, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
inverse->costs += 1;
}
break;
case iro_ia32_Not: {
inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
inverse->nodes[0] = new_bd_ia32_Not(dbg
i
, block, (ir_node*) irn);
inverse->costs += 1;
break;
}
case iro_ia32_Neg: {
inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
inverse->nodes[0] = new_bd_ia32_Neg(dbg
i
, block, (ir_node*) irn);
inverse->costs += 1;
break;
}
...
...
@@ -709,11 +707,11 @@ ir_node *ia32_turn_back_am(ir_node *node)
ir_graph
*
irg
=
get_irn_irg
(
node
);
ir_node
*
block
=
get_nodes_block
(
node
);
ir_node
*
base
=
get_irn_n
(
node
,
n_ia32_base
);
ir_node
*
i
ndex
=
get_irn_n
(
node
,
n_ia32_index
);
ir_node
*
i
dx
=
get_irn_n
(
node
,
n_ia32_index
);
ir_node
*
mem
=
get_irn_n
(
node
,
n_ia32_mem
);
ir_node
*
noreg
;
ir_node
*
load
=
new_bd_ia32_Load
(
dbgi
,
block
,
base
,
i
nde
x
,
mem
);
ir_node
*
load
=
new_bd_ia32_Load
(
dbgi
,
block
,
base
,
i
d
x
,
mem
);
ir_node
*
load_res
=
new_rd_Proj
(
dbgi
,
load
,
mode_Iu
,
pn_ia32_Load_res
);
ia32_copy_am_attrs
(
load
,
node
);
...
...
@@ -787,7 +785,6 @@ static ir_node *flags_remat(ir_node *node, ir_node *after)
case
ia32_AddrModeD
:
/* TODO implement this later... */
panic
(
"found DestAM with flag user %+F this should not happen"
,
node
);
break
;
default:
assert
(
type
==
ia32_Normal
);
break
;
}
...
...
@@ -821,7 +818,7 @@ static void ia32_before_ra(ir_graph *irg)
static
void
transform_to_Load
(
ir_node
*
node
)
{
ir_graph
*
irg
=
get_irn_irg
(
node
);
dbg_info
*
dbg
=
get_irn_dbg_info
(
node
);
dbg_info
*
dbg
i
=
get_irn_dbg_info
(
node
);
ir_node
*
block
=
get_nodes_block
(
node
);
ir_entity
*
ent
=
be_get_frame_entity
(
node
);
ir_mode
*
mode
=
get_irn_mode
(
node
);
...
...
@@ -839,16 +836,16 @@ static void transform_to_Load(ir_node *node)
if
(
mode_is_float
(
spillmode
))
{
if
(
ia32_cg_config
.
use_sse2
)
new_op
=
new_bd_ia32_xLoad
(
dbg
,
block
,
ptr
,
noreg
,
mem
,
spillmode
);
new_op
=
new_bd_ia32_xLoad
(
dbg
i
,
block
,
ptr
,
noreg
,
mem
,
spillmode
);
else
new_op
=
new_bd_ia32_vfld
(
dbg
,
block
,
ptr
,
noreg
,
mem
,
spillmode
);
new_op
=
new_bd_ia32_vfld
(
dbg
i
,
block
,
ptr
,
noreg
,
mem
,
spillmode
);
}
else
if
(
get_mode_size_bits
(
spillmode
)
==
128
)
{
/* Reload 128 bit SSE registers */
new_op
=
new_bd_ia32_xxLoad
(
dbg
,
block
,
ptr
,
noreg
,
mem
);
new_op
=
new_bd_ia32_xxLoad
(
dbg
i
,
block
,
ptr
,
noreg
,
mem
);
}
else
new_op
=
new_bd_ia32_Load
(
dbg
,
block
,
ptr
,
noreg
,
mem
);
new_op
=
new_bd_ia32_Load
(
dbg
i
,
block
,
ptr
,
noreg
,
mem
);
set_ia32_op_type
(
new_op
,
ia32_AddrModeS
);
set_ia32_ls_mode
(
new_op
,
spillmode
);
...
...
@@ -858,7 +855,7 @@ static void transform_to_Load(ir_node *node)
DBG_OPT_RELOAD2LD
(
node
,
new_op
);
proj
=
new_rd_Proj
(
dbg
,
new_op
,
mode
,
pn_ia32_Load_res
);
proj
=
new_rd_Proj
(
dbg
i
,
new_op
,
mode
,
pn_ia32_Load_res
);
if
(
sched_point
)
{
sched_add_after
(
sched_point
,
new_op
);
...
...
@@ -880,7 +877,7 @@ static void transform_to_Load(ir_node *node)
static
void
transform_to_Store
(
ir_node
*
node
)
{
ir_graph
*
irg
=
get_irn_irg
(
node
);
dbg_info
*
dbg
=
get_irn_dbg_info
(
node
);
dbg_info
*
dbg
i
=
get_irn_dbg_info
(
node
);
ir_node
*
block
=
get_nodes_block
(
node
);
ir_entity
*
ent
=
be_get_frame_entity
(
node
);
const
ir_node
*
spillval
=
get_irn_n
(
node
,
n_be_Spill_val
);
...
...
@@ -899,21 +896,21 @@ static void transform_to_Store(ir_node *node)
if
(
mode_is_float
(
mode
))
{
if
(
ia32_cg_config
.
use_sse2
)
{
store
=
new_bd_ia32_xStore
(
dbg
,
block
,
ptr
,
noreg
,
nomem
,
val
);
store
=
new_bd_ia32_xStore
(
dbg
i
,
block
,
ptr
,
noreg
,
nomem
,
val
);
res
=
new_r_Proj
(
store
,
mode_M
,
pn_ia32_xStore_M
);
}
else
{
store
=
new_bd_ia32_vfst
(
dbg
,
block
,
ptr
,
noreg
,
nomem
,
val
,
mode
);
store
=
new_bd_ia32_vfst
(
dbg
i
,
block
,
ptr
,
noreg
,
nomem
,
val
,
mode
);
res
=
new_r_Proj
(
store
,
mode_M
,
pn_ia32_vfst_M
);
}
}
else
if
(
get_mode_size_bits
(
mode
)
==
128
)
{
/* Spill 128 bit SSE registers */
store
=
new_bd_ia32_xxStore
(
dbg
,
block
,
ptr
,
noreg
,
nomem
,
val
);
store
=
new_bd_ia32_xxStore
(
dbg
i
,
block
,
ptr
,
noreg
,
nomem
,
val
);
res
=
new_r_Proj
(
store
,
mode_M
,
pn_ia32_xxStore_M
);
}
else
if
(
get_mode_size_bits
(
mode
)
==
8
)
{
store
=
new_bd_ia32_Store8Bit
(
dbg
,
block
,
ptr
,
noreg
,
nomem
,
val
);
store
=
new_bd_ia32_Store8Bit
(
dbg
i
,
block
,
ptr
,
noreg
,
nomem
,
val
);
res
=
new_r_Proj
(
store
,
mode_M
,
pn_ia32_Store8Bit_M
);
}
else
{
store
=
new_bd_ia32_Store
(
dbg
,
block
,
ptr
,
noreg
,
nomem
,
val
);
store
=
new_bd_ia32_Store
(
dbg
i
,
block
,
ptr
,
noreg
,
nomem
,
val
);
res
=
new_r_Proj
(
store
,
mode_M
,
pn_ia32_Store_M
);
}
...
...
@@ -935,13 +932,13 @@ static void transform_to_Store(ir_node *node)
static
ir_node
*
create_push
(
ir_node
*
node
,
ir_node
*
schedpoint
,
ir_node
*
sp
,
ir_node
*
mem
,
ir_entity
*
ent
)
{
dbg_info
*
dbg
=
get_irn_dbg_info
(
node
);
ir_node
*
block
=
get_nodes_block
(
node
);
ir_graph
*
irg
=
get_irn_irg
(
node
);
ir_node
*
noreg
=
ia32_new_NoReg_gp
(
irg
);
ir_node
*
frame
=
get_irg_frame
(
irg
);
dbg_info
*
dbg
i
=
get_irn_dbg_info
(
node
);
ir_node
*
block
=
get_nodes_block
(
node
);
ir_graph
*
irg
=
get_irn_irg
(
node
);
ir_node
*
noreg
=
ia32_new_NoReg_gp
(
irg
);
ir_node
*
frame
=
get_irg_frame
(
irg
);
ir_node
*
push
=
new_bd_ia32_Push
(
dbg
,
block
,
frame
,
noreg
,
mem
,
noreg
,
sp
);
ir_node
*
push
=
new_bd_ia32_Push
(
dbg
i
,
block
,
frame
,
noreg
,
mem
,
noreg
,
sp
);
set_ia32_frame_ent
(
push
,
ent
);
set_ia32_use_frame
(
push
);
...
...
@@ -955,13 +952,13 @@ static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_
static
ir_node
*
create_pop
(
ir_node
*
node
,
ir_node
*
schedpoint
,
ir_node
*
sp
,
ir_entity
*
ent
)
{
dbg_info
*
dbg
=
get_irn_dbg_info
(
node
);
dbg_info
*
dbg
i
=
get_irn_dbg_info
(
node
);
ir_node
*
block
=
get_nodes_block
(
node
);
ir_graph
*
irg
=
get_irn_irg
(
node
);
ir_node
*
noreg
=
ia32_new_NoReg_gp
(
irg
);
ir_node
*
frame
=
get_irg_frame
(
irg
);
ir_node
*
pop
=
new_bd_ia32_PopMem
(
dbg
,
block
,
frame
,
noreg
,
ir_node
*
pop
=
new_bd_ia32_PopMem
(
dbg
i
,
block
,
frame
,
noreg
,
get_irg_no_mem
(
irg
),
sp
);
set_ia32_frame_ent
(
pop
,
ent
);
...
...
@@ -977,12 +974,12 @@ static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_e
static
ir_node
*
create_spproj
(
ir_node
*
node
,
ir_node
*
pred
,
int
pos
)
{
dbg_info
*
dbg
=
get_irn_dbg_info
(
node
);
ir_mode
*
spmode
=
mode_Iu
;
dbg_info
*
dbg
i
=
get_irn_dbg_info
(
node
);
ir_mode
*
spmode
=
mode_Iu
;
const
arch_register_t
*
spreg
=
&
ia32_registers
[
REG_ESP
];
ir_node
*
sp
;
sp
=
new_rd_Proj
(
dbg
,
pred
,
spmode
,
pos
);
sp
=
new_rd_Proj
(
dbg
i
,
pred
,
spmode
,
pos
);
arch_set_irn_register
(
sp
,
spreg
);
return
sp
;
...
...
@@ -1662,8 +1659,6 @@ static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
static
void
ia32_get_call_abi
(
const
void
*
self
,
ir_type
*
method_type
,
be_abi_call_t
*
abi
)
{
ir_type
*
tp
;
ir_mode
*
mode
;
unsigned
cc
;
int
n
,
i
,
regnum
;
int
pop_amount
=
0
;
...
...
@@ -1701,11 +1696,10 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type,
n
=
get_method_n_params
(
method_type
);
for
(
i
=
regnum
=
0
;
i
<
n
;
i
++
)
{
ir_mode
*
mode
;
const
arch_register_t
*
reg
=
NULL
;
const
arch_register_t
*
reg
=
NULL
;
ir_type
*
tp
=
get_method_param_type
(
method_type
,
i
);
ir_mode
*
mode
=
get_type_mode
(
tp
);
tp
=
get_method_param_type
(
method_type
,
i
);
mode
=
get_type_mode
(
tp
);
if
(
mode
!=
NULL
)
{
reg
=
ia32_get_RegParam_reg
(
cc
,
regnum
,
mode
);
}
...
...
@@ -1740,8 +1734,8 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type,
/* In case of 64bit returns, we will have two 32bit values */
if
(
n
==
2
)
{
tp
=
get_method_res_type
(
method_type
,
0
);
mode
=
get_type_mode
(
tp
);
ir_type
*
tp
=
get_method_res_type
(
method_type
,
0
);
ir_mode
*
mode
=
get_type_mode
(
tp
);
assert
(
!
mode_is_float
(
mode
)
&&
"two FP results not supported"
);
...
...
@@ -1754,11 +1748,10 @@ static void ia32_get_call_abi(const void *self, ir_type *method_type,
be_abi_call_res_reg
(
abi
,
1
,
&
ia32_registers
[
REG_EDX
],
ABI_CONTEXT_BOTH
);
}
else
if
(
n
==
1
)
{
ir_type
*
tp
=
get_method_res_type
(
method_type
,
0
);
ir_mode
*
mode
=
get_type_mode
(
tp
);
const
arch_register_t
*
reg
;
tp
=
get_method_res_type
(
method_type
,
0
);
assert
(
is_atomic_type
(
tp
));
mode
=
get_type_mode
(
tp
);
reg
=
mode_is_float
(
mode
)
?
&
ia32_registers
[
REG_VF0
]
:
&
ia32_registers
[
REG_EAX
];
...
...
@@ -2227,8 +2220,6 @@ void be_init_arch_ia32(void)
lc_opt_add_table
(
ia32_grp
,
ia32_options
);
be_register_isa_if
(
"ia32"
,
&
ia32_isa_if
);
FIRM_DBG_REGISTER
(
dbg
,
"firm.be.ia32.cg"
);
ia32_init_emitter
();
ia32_init_finish
();
ia32_init_optimize
();
...
...
ir/be/ia32/ia32_common_transform.c
View file @
fc81b817
...
...
@@ -371,11 +371,9 @@ static void parse_asm_constraints(constraint_t *constraint, const char *c,
case
'e'
:
/* not available in 32 bit mode */
panic
(
"unsupported asm constraint '%c' found in (%+F)"
,
*
c
,
current_ir_graph
);
break
;
default:
panic
(
"unknown asm constraint '%c' found in (%+F)"
,
*
c
,
current_ir_graph
);
break
;
}
++
c
;
}
...
...
@@ -562,7 +560,6 @@ ir_node *ia32_gen_ASM(ir_node *node)
}
if
(
input
==
NULL
)
{
ir_node
*
pred
=
get_irn_n
(
node
,
i
);
input
=
get_new_node
(
pred
);
if
(
parsed_constraint
.
cls
==
NULL
...
...
@@ -597,8 +594,8 @@ ir_node *ia32_gen_ASM(ir_node *node)
/* count inputs which are real values (and not memory) */
value_arity
=
0
;
for
(
i
=
0
;
i
<
arity
;
++
i
)
{
ir_node
*
in
=
get_irn_n
(
node
,
i
);
if
(
get_irn_mode
(
in
)
==
mode_M
)
ir_node
*
node_
in
=
get_irn_n
(
node
,
i
);
if
(
get_irn_mode
(
node_
in
)
==
mode_M
)
continue
;
++
value_arity
;
}
...
...
@@ -621,7 +618,6 @@ ir_node *ia32_gen_ASM(ir_node *node)
int
o
;
bitset_t
*
used_ins
=
bitset_alloca
(
arity
);
for
(
o
=
0
;
o
<
out_arity
;
++
o
)
{
int
i
;
const
arch_register_req_t
*
outreq
=
out_reg_reqs
[
o
];
if
(
outreq
->
cls
==
NULL
)
{
...
...
@@ -665,7 +661,6 @@ ir_node *ia32_gen_ASM(ir_node *node)
++
arity
;
}
}
else
{
int
i
;
bitset_t
*
used_outs
=
bitset_alloca
(
out_arity
);
int
orig_out_arity
=
out_arity
;
for
(
i
=
0
;
i
<
arity
;
++
i
)
{
...
...
ir/be/ia32/ia32_emitter.c
View file @
fc81b817
...
...
@@ -557,8 +557,8 @@ void ia32_emit_am(const ir_node *node)
int
offs
=
get_ia32_am_offs_int
(
node
);
ir_node
*
base
=
get_irn_n
(
node
,
n_ia32_base
);
int
has_base
=
!
is_ia32_NoReg_GP
(
base
);
ir_node
*
i
ndex
=
get_irn_n
(
node
,
n_ia32_index
);
int
has_index
=
!
is_ia32_NoReg_GP
(
i
nde
x
);
ir_node
*
i
dx
=
get_irn_n
(
node
,
n_ia32_index
);
int
has_index
=
!
is_ia32_NoReg_GP
(
i
d
x
);
/* just to be sure... */
assert
(
!
is_ia32_use_frame
(
node
)
||
get_ia32_frame_ent
(
node
)
!=
NULL
);
...
...
@@ -708,7 +708,6 @@ emit_AM:
assert
(
get_ia32_op_type
(
node
)
==
ia32_Normal
);
goto
emit_S
;
}
break
;
default:
goto
unknown
;
}
...
...
@@ -1385,8 +1384,8 @@ static void emit_ia32_Conv_FP2FP(const ir_node *node)
*/
static
void
emit_ia32_Conv_I2I
(
const
ir_node
*
node
)
{
ir_mode
*
smaller_mode
=
get_ia32_ls_mode
(
node
);
int
signed_mode
=
mode_is_signed
(
smaller_mode
);
ir_mode
*
smaller_mode
=
get_ia32_ls_mode
(
node
);
int
signed_mode
=
mode_is_signed
(
smaller_mode
);
const
char
*
sign_suffix
;
assert
(
!
mode_is_float
(
smaller_mode
));
...
...
@@ -1814,10 +1813,10 @@ static int should_align_block(const ir_node *block)
*/
static
void
ia32_emit_block_header
(
ir_node
*
block
)
{
ir_graph
*
irg
=
current_ir_graph
;
ir_graph
*
irg
=
current_ir_graph
;
int
need_label
=
block_needs_label
(
block
);
i
nt
i
,
arity
;
i
r_exec_freq
*
exec_freq
=
be_get_irg_exec_freq
(
irg
)
;
i
r_exec_freq
*
exec_freq
=
be_get_irg_exec_freq
(
irg
)
;
i
nt
arity
;
if
(
block
==
get_irg_end_block
(
irg
))
return
;
...
...
@@ -1867,6 +1866,7 @@ static void ia32_emit_block_header(ir_node *block)
if
(
arity
<=
0
)
{
be_emit_cstring
(
" none"
);
}
else
{
int
i
;
for
(
i
=
0
;
i
<
arity
;
++
i
)
{
ir_node
*
predblock
=
get_Block_cfgpred_block
(
block
,
i
);
be_emit_irprintf
(
" %d"
,
get_irn_node_nr
(
predblock
));
...
...
@@ -1996,14 +1996,14 @@ void ia32_gen_routine(ir_graph *irg)
Those are ascending with ascending addresses. */
qsort
(
exc_list
,
ARR_LEN
(
exc_list
),
sizeof
(
exc_list
[
0
]),
cmp_exc_entry
);
{
size_t
i
;
size_t
e
;
for
(
i
=
0
;
i
<
ARR_LEN
(
exc_list
);
++
i
)
{
for
(
e
=
0
;
e
<
ARR_LEN
(
exc_list
);
++
e
)
{
be_emit_cstring
(
"
\t
.long "
);
ia32_emit_exc_label
(
exc_list
[
i
].
exc_instr
);
ia32_emit_exc_label
(
exc_list
[
e
].
exc_instr
);
be_emit_char
(
'\n'
);
be_emit_cstring
(
"
\t
.long "
);
be_gas_emit_block_name
(
exc_list
[
i
].
block
);
be_gas_emit_block_name
(
exc_list
[
e
].
block
);
be_emit_char
(
'\n'
);
}
}
...
...
@@ -2209,8 +2209,8 @@ static void bemit_mod_am(unsigned reg, const ir_node *node)
int
offs
=
get_ia32_am_offs_int
(
node
);
ir_node
*
base
=
get_irn_n
(
node
,
n_ia32_base
);
int
has_base
=
!
is_ia32_NoReg_GP
(
base
);
ir_node
*
i
ndex
=
get_irn_n
(
node
,
n_ia32_index
);
int
has_index
=
!
is_ia32_NoReg_GP
(
i
nde
x
);
ir_node
*
i
dx
=
get_irn_n
(
node
,
n_ia32_index
);
int
has_index
=
!
is_ia32_NoReg_GP
(
i
d
x
);
unsigned
modrm
=
0
;
unsigned
sib
=
0
;
unsigned
emitoffs
=
0
;
...
...
@@ -2245,7 +2245,7 @@ static void bemit_mod_am(unsigned reg, const ir_node *node)
/* Determine if we need a SIB byte. */
if
(
has_index
)
{
const
arch_register_t
*
reg_index
=
arch_get_irn_register
(
i
nde
x
);
const
arch_register_t
*
reg_index
=
arch_get_irn_register
(
i
d
x
);
int
scale
=
get_ia32_am_scale
(
node
);
assert
(
scale
<
4
);
/* R/M set to ESP means SIB in 32bit mode. */
...
...
@@ -3068,8 +3068,8 @@ static void bemit_load(const ir_node *node)
if
(
out
->
index
==
REG_GP_EAX
)
{
ir_node
*
base
=
get_irn_n
(
node
,
n_ia32_base
);
int
has_base
=
!
is_ia32_NoReg_GP
(
base
);
ir_node
*
i
ndex
=
get_irn_n
(
node
,
n_ia32_index
);
int
has_index
=
!
is_ia32_NoReg_GP
(
i
nde
x
);
ir_node
*
i
dx
=
get_irn_n
(
node
,
n_ia32_index
);
int
has_index
=
!
is_ia32_NoReg_GP
(
i
d
x
);
if
(
!
has_base
&&
!
has_index
)
{
ir_entity
*
ent
=
get_ia32_am_sc
(
node
);
int
offs
=
get_ia32_am_offs_int
(
node
);
...
...
@@ -3113,8 +3113,8 @@ static void bemit_store(const ir_node *node)
if
(
in
->
index
==
REG_GP_EAX
)
{
ir_node
*
base
=
get_irn_n
(
node
,
n_ia32_base
);
int
has_base
=
!
is_ia32_NoReg_GP
(
base
);
ir_node
*
i
ndex
=
get_irn_n
(
node
,
n_ia32_index
);
int
has_index
=
!
is_ia32_NoReg_GP
(
i
nde
x
);
ir_node
*
i
dx
=
get_irn_n
(
node
,
n_ia32_index
);
int
has_index
=
!
is_ia32_NoReg_GP
(
i
d
x
);
if
(
!
has_base
&&
!
has_index
)
{
ir_entity
*
ent
=
get_ia32_am_sc
(
node
);
int
offs
=
get_ia32_am_offs_int
(
node
);
...
...
ir/be/ia32/ia32_finish.c
View file @
fc81b817
...
...
@@ -58,7 +58,7 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn)
ir_graph
*
irg
;
ir_node
*
in1
,
*
in2
,
*
noreg
,
*
nomem
,
*
res
;
ir_node
*
noreg_fp
,
*
block
;
dbg_info
*
dbg
;
dbg_info
*
dbg
i
;
const
arch_register_t
*
in1_reg
,
*
in2_reg
,
*
out_reg
;
/* fix_am will solve this for AddressMode variants */
...
...
@@ -83,7 +83,7 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn)
return
;
block
=
get_nodes_block
(
irn
);
dbg
=
get_irn_dbg_info
(
irn
);
dbg
i
=
get_irn_dbg_info
(
irn
);
/* generate the neg src2 */
if
(
is_ia32_xSub
(
irn
))
{
...
...
@@ -93,7 +93,7 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn)
assert
(
get_irn_mode
(
irn
)
!=
mode_T
);
res
=
new_bd_ia32_xXor
(
dbg
,
block
,
noreg
,
noreg
,
nomem
,
in2
,
noreg_fp
);
res
=
new_bd_ia32_xXor
(
dbg
i
,
block
,
noreg
,
noreg
,
nomem
,
in2
,
noreg_fp
);
size
=
get_mode_size_bits
(
op_mode
);
entity
=
ia32_gen_fp_known_const
(
size
==
32
?
ia32_SSIGN
:
ia32_DSIGN
);
set_ia32_am_sc
(
res
,
entity
);
...
...
@@ -106,7 +106,7 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn)
sched_add_before
(
irn
,
res
);
/* generate the add */
res
=
new_bd_ia32_xAdd
(
dbg
,
block
,
noreg
,
noreg
,
nomem
,
res
,
in1
);
res
=
new_bd_ia32_xAdd
(
dbg
i
,
block
,
noreg
,
noreg
,
nomem
,
res
,
in1
);
set_ia32_ls_mode
(
res
,
get_ia32_ls_mode
(
irn
));
/* exchange the add and the sub */
...
...
@@ -136,14 +136,14 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn)
}
if
(
flags_proj
==
NULL
)
{
res
=
new_bd_ia32_Neg
(
dbg
,
block
,
in2
);
res
=
new_bd_ia32_Neg
(
dbg
i
,
block
,
in2
);
arch_set_irn_register
(
res
,
in2_reg
);
/* add to schedule */
sched_add_before
(
irn
,
res
);
/* generate the add */
res
=
new_bd_ia32_Add
(
dbg
,
block
,
noreg
,
noreg
,
nomem
,
res
,
in1
);
res
=
new_bd_ia32_Add
(
dbg
i
,
block
,
noreg
,
noreg
,
nomem
,
res
,
in1
);
arch_set_irn_register
(
res
,
out_reg
);
set_ia32_commutative
(
res
);
...
...
@@ -165,15 +165,15 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn)
*
* a + -b = a + (~b + 1) would set the carry flag IF a == b ...
*/
nnot
=
new_bd_ia32_Not
(
dbg
,
block
,
in2
);
nnot
=
new_bd_ia32_Not
(
dbg
i
,
block
,
in2
);
arch_set_irn_register
(
nnot
,
in2_reg
);
sched_add_before
(
irn
,
nnot
);
stc
=
new_bd_ia32_Stc
(
dbg
,
block
);
stc
=
new_bd_ia32_Stc
(
dbg
i
,
block
);
arch_set_irn_register
(
stc
,
&
ia32_registers
[
REG_EFLAGS
]);
sched_add_before
(
irn
,
stc
);
adc
=
new_bd_ia32_Adc
(
dbg
,
block
,
noreg
,
noreg
,
nomem
,
nnot
,
in1
,
stc
);
adc
=
new_bd_ia32_Adc
(
dbg
i
,
block
,
noreg
,
noreg
,
nomem
,
nnot
,
in1
,
stc
);
arch_set_irn_register
(
adc
,
out_reg
);
sched_add_before
(
irn
,
adc
);
...
...
@@ -181,7 +181,7 @@ static void ia32_transform_sub_to_neg_add(ir_node *irn)
adc_flags
=
new_r_Proj
(
adc
,
mode_Iu
,
pn_ia32_Adc_flags
);
arch_set_irn_register
(
adc_flags
,
&
ia32_registers
[
REG_EFLAGS
]);
cmc
=
new_bd_ia32_Cmc
(
dbg
,
block
,
adc_flags
);
cmc
=
new_bd_ia32_Cmc
(
dbg
i
,
block
,
adc_flags
);
arch_set_irn_register
(
cmc
,
&
ia32_registers
[
REG_EFLAGS
]);
sched_add_before
(
irn
,
cmc
);
...
...
@@ -287,14 +287,14 @@ static void assure_should_be_same_requirements(ir_node *node)
uses_out_reg_pos
=
-
1
;
for
(
i2
=
0
;
i2
<
arity
;
++
i2
)
{
ir_node
*
in
=
get_irn_n
(
node
,
i2
);
const
arch_register_t
*
in_reg
;
const
arch_register_t
*
other_
in_reg
;
if
(
!
mode_is_data
(
get_irn_mode
(
in
)))
continue
;
in_reg
=
arch_get_irn_register
(
in
);
other_
in_reg
=
arch_get_irn_register
(
in
);
if
(
in_reg
!=
out_reg
)
if
(
other_
in_reg
!=
out_reg
)
continue
;
if
(
uses_out_reg
!=
NULL
&&
in
!=
uses_out_reg
)
{
...
...
ir/be/ia32/ia32_fpu.c
View file @
fc81b817
...
...
@@ -87,7 +87,6 @@ static void create_fpcw_entities(void)
static
ir_node
*
create_fpu_mode_spill
(
void
*
env
,
ir_node
*
state
,
int
force
,
ir_node
*
after
)
{
ir_node
*
spill
=
NULL
;
(
void
)
env
;
/* we don't spill the fpcw in unsafe mode */
...
...
@@ -107,17 +106,18 @@ static ir_node *create_fpu_mode_spill(void *env, ir_node *state, int force,
ir_node
*
noreg
=
ia32_new_NoReg_gp
(
irg
);
ir_node
*
nomem
=
get_irg_no_mem
(
irg
);
ir_node
*
frame
=
get_irg_frame
(
irg
);
spill
=
new_bd_ia32_FnstCW
(
NULL
,
block
,
frame
,
noreg
,
nomem
,
state
);
ir_node
*
spill
=
new_bd_ia32_FnstCW
(
NULL
,
block
,
frame
,
noreg
,
nomem
,
state
);
set_ia32_op_type
(
spill
,
ia32_AddrModeD
);
/* use mode_Iu, as movl has a shorter opcode than movw */
set_ia32_ls_mode
(
spill
,
mode_Iu
);
set_ia32_use_frame
(
spill
);
sched_add_after
(
skip_Proj
(
after
),
spill
);
return
spill
;
}
return
spill
;
return
NULL
;
}
static
ir_node
*
create_fldcw_ent
(
ir_node
*
block
,
ir_entity
*
entity
)
...
...
ir/be/ia32/ia32_intrinsics.c
View file @
fc81b817
...
...
@@ -67,15 +67,15 @@ void ia32_handle_intrinsics(void)
/**
* Reroute edges from the pn_Call_T_result proj of a call.
*
* @param proj
the pn_Call_T_result Proj
* @param l_res the lower 32 bit result
* @param h_res the upper 32 bit result or NULL
* @param
res
proj the pn_Call_T_result Proj
* @param l_res
the lower 32 bit result
* @param h_res
the upper 32 bit result or NULL
*/
static
void
reroute_result
(
ir_node
*
proj
,
ir_node
*
l_res
,
ir_node
*
h_res
)
static
void
reroute_result
(
ir_node
*
res
proj
,
ir_node
*
l_res
,
ir_node
*
h_res
)
{
const
ir_edge_t
*
edge
,
*
next
;
foreach_out_edge_safe
(
proj
,
edge
,
next
)
{
foreach_out_edge_safe
(
res
proj
,
edge
,
next
)
{
ir_node
*
proj
=
get_edge_src_irn
(
edge
);
long
pn
=
get_Proj_proj
(
proj
);
...
...
ir/be/ia32/ia32_optimize.c
View file @
fc81b817
...
...
@@ -314,16 +314,16 @@ static void peephole_ia32_Test(ir_node *node)
if
((
offset
&
0xFFFFFF00
)
==
0
)
{