Commit fef8dc3e authored by Christoph Mallon's avatar Christoph Mallon
Browse files

besched: Add and use sched_replace().

parent d7f28dfa
......@@ -150,8 +150,7 @@ static void transform_Reload(ir_node *node)
ir_node *load;
load = new_bd_amd64_Load(dbgi, block, ptr, mem, entity);
sched_add_before(node, load);
sched_remove(node);
sched_replace(node, load);
proj = new_rd_Proj(dbgi, load, mode, pn_amd64_Load_res);
......@@ -174,8 +173,7 @@ static void transform_Spill(ir_node *node)
ir_node *store;
store = new_bd_amd64_Store(dbgi, block, ptr, val, mem, entity);
sched_add_before(node, store);
sched_remove(node);
sched_replace(node, store);
exchange(node, store);
}
......
......@@ -192,8 +192,7 @@ static void transform_Reload(ir_node *node)
ir_node *load;
load = new_bd_arm_Ldr(dbgi, block, ptr, mem, mode, entity, false, 0, true);
sched_add_before(node, load);
sched_remove(node);
sched_replace(node, load);
proj = new_rd_Proj(dbgi, load, mode, pn_arm_Ldr_res);
......@@ -217,8 +216,7 @@ static void transform_Spill(ir_node *node)
store = new_bd_arm_Str(dbgi, block, ptr, val, mem, mode, entity, false, 0,
true);
sched_add_before(node, store);
sched_remove(node);
sched_replace(node, store);
exchange(node, store);
}
......
......@@ -790,10 +790,9 @@ void assure_constraints(ir_graph *irg)
ir_node *keep;
keep = be_new_Keep(get_nodes_block(cp), n, get_irn_in(cp) + 1);
sched_add_before(cp, keep);
sched_replace(cp, keep);
/* Set all ins (including the block) of the CopyKeep BAD to keep the verifier happy. */
sched_remove(cp);
kill_node(cp);
}
}
......
......@@ -143,7 +143,23 @@ void sched_remove(ir_node *irn)
info->prev = NULL;
}
void sched_replace(ir_node *const old, ir_node *const irn)
{
assert(sched_is_scheduled(old));
assert(!sched_is_scheduled(irn));
sched_info_t *const old_info = get_irn_sched_info(old);
sched_info_t *const irn_info = get_irn_sched_info(irn);
*irn_info = *old_info;
old_info->prev = NULL;
old_info->next = NULL;
ir_node *const prev = irn_info->prev;
ir_node *const next = irn_info->next;
get_irn_sched_info(prev)->next = irn;
get_irn_sched_info(next)->prev = irn;
}
static be_module_list_entry_t *schedulers;
static schedule_func scheduler;
......
......@@ -152,6 +152,11 @@ static inline void sched_reset(ir_node *node)
*/
void sched_remove(ir_node *irn);
/**
* Remove @p old from the schedule and put @p irn in its place.
*/
void sched_replace(ir_node *old, ir_node *irn);
/**
* Checks, if one node is scheduled before another.
* @param n1 A node.
......
......@@ -698,8 +698,7 @@ static void transform_to_Load(ir_node *node)
proj = new_rd_Proj(dbgi, new_op, mode, pn_ia32_Load_res);
sched_add_before(node, new_op);
sched_remove(node);
sched_replace(node, new_op);
/* copy the register from the old node to the new Load */
reg = arch_get_irn_register(node);
......@@ -756,9 +755,7 @@ static void transform_to_Store(ir_node *node)
SET_IA32_ORIG_NODE(store, node);
DBG_OPT_SPILL2ST(node, store);
sched_add_before(node, store);
sched_remove(node);
sched_replace(node, store);
exchange(node, res);
}
......@@ -889,7 +886,7 @@ static void transform_MemPerm(ir_node *node)
in[0] = sp;
keep = be_new_Keep(block, 1, in);
sched_add_before(node, keep);
sched_replace(node, keep);
/* exchange memprojs */
foreach_out_edge_safe(node, edge) {
......@@ -903,7 +900,6 @@ static void transform_MemPerm(ir_node *node)
}
/* remove memperm */
sched_remove(node);
kill_node(node);
}
......
......@@ -187,14 +187,13 @@ carry:
/* exchange the add and the sub */
edges_reroute(irn, res);
sched_add_before(irn, res);
sched_replace(irn, res);
set_irn_mode(res, get_irn_mode(irn));
SET_IA32_ORIG_NODE(res, irn);
/* remove the old sub */
sched_remove(irn);
kill_node(irn);
DBG_OPT_SUB2NEGADD(irn, res);
......
......@@ -1350,10 +1350,8 @@ static int sim_Copy(x87_state *state, ir_node *n)
* instruction, but we would have to rerun all the simulation to get
* this correct...
*/
ir_node *const next = sched_next(n);
sched_remove(n);
sched_replace(n, node);
exchange(n, node);
sched_add_before(next, node);
if (get_irn_n_edges(pred) == 0) {
keep_float_node_alive(pred);
......
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