Do not store up to three registers for an instruction.
Instead only store the explicit register operand and whether the operands are permuted and/or the result is to be placed in the explicit register operand or st0.

Let a flag and the emitter handle printing the pop variant.

Let a flag and the emitter handle printing the pop variant.

Let a flag and the emitter handle printing the pop variant.

Let the emitter handle printing the r by checking the assigned registers.

Simulating it as normal binop does only work in one special case.
It lacks the reverse form and selecting the second operand register.
So in many cases invalid code was generated silently.

When hard-coding the *, invalid assembler gets emitted if an immediate ends up as ia32_IJmp operand.

memops are nodes that have memory inputs, you can generically query them
for their memory input. We can also get rid of get_fragile_op_mem in
favor of get_memop_mem.

This is the new way of handling switch-jumps. The node contains a table
which maps (ranges of) input values to proj numbers. Compared to a
Cond-node this results in a clean consecutive sequence of Proj numbers
(no searching for a free number for the default_pn anymore) and allows
factoring multiple cases jumping to the same block in a single Proj
(though we still need the optimisation in cfopt for that).

The main change here is splitting new_ir_mode into new_int_mode,
new_reference_mode and new_float_mode. You can now specify
mantissa+exponent size in new_float_mode. This also changes:

- x86 80bit-FP mode is NOT a ieee754 don't put "ieee754" into functions
  names that can also handle x86 80bit fps
- Move ieee_descriptor_t from tarval module into ir_mode struct
  (and rename to float_descriptor_t)
- Introduce mode_Q which represents binary128 from ieee754
- You can ask float modes for mantissa/exponent sizes now
- Fix endianess when emitting big float values in begnuas
- A bunch of long double fixes in ia32: the mode there has 10bytes
  (80bit) but the variables typically are 12 or 16 byte big
- This fixes some problems of sparc binary128 handling

It is just an unnecessary node, which the middleend does not understand and therefore cannot optimize.

Some backends create nodes in their lower_for_target phases already.
These nodes are placeholders for real backend nodes later, in contrast
they do not have register requirements or backend attributes. Simplified
this by allowing custom dumpers for them and leaving out the backend
node structs.

This tries to get the names in a consistent format. We basically have 2
views on register allocation/constraints now:

1) Register Requirements and Assigments are per-instruction. Each
   instruction has requirements on its inputs and outputs, register get
   assigned for outputs of an instruction (assignment is an attribute of
   an instruction, not of the Proj-nodes).
   The internal datastructures model this form!

   The functions here have the form:
     arch_get_irn_register_req_in(node, input_nr)
     arch_get_irn_register_in(node, input_nr)
     arch_get_irn_register_req_out(node, output_nr)
     arch_set_irn_register_out(node, output_nr, register)

2) Register Requirements and Assignments are on firm-values. This view
   allows to query/assign requirements and registers at the Proj nodes
   instead of the repsective predecessors.
   This is a convenience interface modeled on top of the other!

   The functions have the form:
     arch_get_irn_register_req(node)
     arch_get_irn_register(node)
     arch_set_irn_register(node, register)

This should fix 403.gcc.
A SBB with AM could not fulfill its should_be_same contraint, so the AM gets split from the SBB.
The Load of the AM gets assigned the out register of the SBB, which violates the !in_r5 constraint of the SBB.
Therefore it's necessary to turn the SBB into NOT+ADC.

The callee/caller saved information is not constant accross different
ABI's, so don't make it constant. Instead, all BE that still use beabi
provide a callback now.
This allows to implement support for x64_64/Win32 and is a necessary step
for the combined x86 BE.

- The pns of X_regular and X_except are annotated in the opcode now.
- The memory input is annotated in the opcode now
- only nodes with X_regular, X_except are marked fragile

We can still use ia32 ShlD, ShrD functions by matching Or(Shl,Shr)
patterns in the ia32 transformer.

add unknown_jump opflag for the special case of a jump where we can't directly influence the destination and can't predict/change them

[r28391]

reworked ia32 condition code handling, remove backend Bound support (really someone should lower it before the backend

[r28386]

[r28139]

[r28127]