1. 15 Nov, 2012 1 commit
    • Christoph Mallon's avatar
      x87: Simplify x87 code generation. · 0dd7a06d
      Christoph Mallon authored
      Do not store up to three registers for an instruction.
      Instead only store the explicit register operand and whether the operands are permuted and/or the result is to be placed in the explicit register operand or st0.
  2. 12 Nov, 2012 5 commits
  3. 11 Nov, 2012 1 commit
  4. 29 Oct, 2012 1 commit
  5. 22 Oct, 2012 1 commit
  6. 23 Jul, 2012 1 commit
  7. 18 Jul, 2012 1 commit
  8. 19 Jun, 2012 3 commits
  9. 25 Apr, 2012 1 commit
  10. 17 Feb, 2012 1 commit
  11. 21 Dec, 2011 1 commit
  12. 07 Dec, 2011 1 commit
    • Matthias Braun's avatar
      correctly implement memop handling · 9fbdcb82
      Matthias Braun authored
      memops are nodes that have memory inputs, you can generically query them
      for their memory input. We can also get rid of get_fragile_op_mem in
      favor of get_memop_mem.
  13. 10 Nov, 2011 2 commits
  14. 02 Nov, 2011 1 commit
    • Matthias Braun's avatar
      introduce Switch node · 1c89dc2a
      Matthias Braun authored
      This is the new way of handling switch-jumps. The node contains a table
      which maps (ranges of) input values to proj numbers. Compared to a
      Cond-node this results in a clean consecutive sequence of Proj numbers
      (no searching for a free number for the default_pn anymore) and allows
      factoring multiple cases jumping to the same block in a single Proj
      (though we still need the optimisation in cfopt for that).
  15. 27 Oct, 2011 1 commit
    • Matthias Braun's avatar
      ir_mode: simplify interface, improve float-mode handling · e3b765fc
      Matthias Braun authored
      The main change here is splitting new_ir_mode into new_int_mode,
      new_reference_mode and new_float_mode. You can now specify
      mantissa+exponent size in new_float_mode. This also changes:
      - x86 80bit-FP mode is NOT a ieee754 don't put "ieee754" into functions
        names that can also handle x86 80bit fps
      - Move ieee_descriptor_t from tarval module into ir_mode struct
        (and rename to float_descriptor_t)
      - Introduce mode_Q which represents binary128 from ieee754
      - You can ask float modes for mantissa/exponent sizes now
      - Fix endianess when emitting big float values in begnuas
      - A bunch of long double fixes in ia32: the mode there has 10bytes
        (80bit) but the variables typically are 12 or 16 byte big
      - This fixes some problems of sparc binary128 handling
  16. 25 Oct, 2011 1 commit
  17. 15 Sep, 2011 1 commit
    • Matthias Braun's avatar
      some cleanups for middleend node creation in backends · 799d89c9
      Matthias Braun authored
      Some backends create nodes in their lower_for_target phases already.
      These nodes are placeholders for real backend nodes later, in contrast
      they do not have register requirements or backend attributes. Simplified
      this by allowing custom dumpers for them and leaving out the backend
      node structs.
  18. 15 Aug, 2011 2 commits
    • Matthias Braun's avatar
      big refactoring of arch_XXX functions · 41dc42af
      Matthias Braun authored
      This tries to get the names in a consistent format. We basically have 2
      views on register allocation/constraints now:
      1) Register Requirements and Assigments are per-instruction. Each
         instruction has requirements on its inputs and outputs, register get
         assigned for outputs of an instruction (assignment is an attribute of
         an instruction, not of the Proj-nodes).
         The internal datastructures model this form!
         The functions here have the form:
           arch_get_irn_register_req_in(node, input_nr)
           arch_get_irn_register_in(node, input_nr)
           arch_get_irn_register_req_out(node, output_nr)
           arch_set_irn_register_out(node, output_nr, register)
      2) Register Requirements and Assignments are on firm-values. This view
         allows to query/assign requirements and registers at the Proj nodes
         instead of the repsective predecessors.
         This is a convenience interface modeled on top of the other!
         The functions have the form:
           arch_set_irn_register(node, register)
    • Matthias Braun's avatar
  19. 27 Jul, 2011 1 commit
    • Christoph Mallon's avatar
      Extend the NOT+ADC-trick (sic) for SUB to SBB. · 7461eb0c
      Christoph Mallon authored
      This should fix 403.gcc.
      A SBB with AM could not fulfill its should_be_same contraint, so the AM gets split from the SBB.
      The Load of the AM gets assigned the out register of the SBB, which violates the !in_r5 constraint of the SBB.
      Therefore it's necessary to turn the SBB into NOT+ADC.
  20. 11 Jun, 2011 1 commit
  21. 08 Jun, 2011 1 commit
    • Michael Beck's avatar
      Removed the callee/caller saved flag from register specification. · ad8c4178
      Michael Beck authored
      The callee/caller saved information is not constant accross different
      ABI's, so don't make it constant. Instead, all BE that still use beabi
      provide a callback now.
      This allows to implement support for x64_64/Win32 and is a necessary step
      for the combined x86 BE.
  22. 01 Jun, 2011 1 commit
  23. 25 May, 2011 1 commit
    • Matthias Braun's avatar
      cleanup fragile op handling · 99f23ed8
      Matthias Braun authored
      - The pns of X_regular and X_except are annotated in the opcode now.
      - The memory input is annotated in the opcode now
      - only nodes with X_regular, X_except are marked fragile
  24. 23 May, 2011 1 commit
  25. 28 Apr, 2011 1 commit
  26. 08 Apr, 2011 1 commit
  27. 30 Mar, 2011 1 commit
  28. 22 Mar, 2011 1 commit
  29. 17 Feb, 2011 2 commits
  30. 14 Nov, 2010 1 commit
  31. 04 Nov, 2010 1 commit