- 27 Jul, 2011 3 commits
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Christoph Mallon authored
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Christoph Mallon authored
This should fix 403.gcc. A SBB with AM could not fulfill its should_be_same contraint, so the AM gets split from the SBB. The Load of the AM gets assigned the out register of the SBB, which violates the !in_r5 constraint of the SBB. Therefore it's necessary to turn the SBB into NOT+ADC.
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Christoph Mallon authored
Correct inaccurate comment: The only corner case of wrong CF in NEG+ADD as replacement for SUB is if both operands are zero.
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- 16 Jun, 2011 1 commit
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Matthias Braun authored
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- 23 May, 2011 1 commit
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Andreas Zwinkau authored
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- 13 Apr, 2011 1 commit
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Matthias Braun authored
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- 08 Apr, 2011 1 commit
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Matthias Braun authored
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- 01 Dec, 2010 1 commit
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Matthias Braun authored
use a 'low-tech' solution for emitting 8- and 16-bit register names. This also fixes a recently introduced bug in ia32_build_8bit_reg_map_high [r28168]
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- 14 Nov, 2010 1 commit
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Michael Beck authored
[r28139]
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- 04 Nov, 2010 1 commit
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Matthias Braun authored
[r28127]
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- 06 Oct, 2010 2 commits
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Matthias Braun authored
[r28038]
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Matthias Braun authored
[r28037]
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- 22 Sep, 2010 1 commit
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Matthias Braun authored
eliminate the unnecessary and especially confusing concept of a 'code_generator' an isa-interface is enough [r28009]
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- 15 Mar, 2010 1 commit
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Matthias Braun authored
[r27297]
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- 10 Mar, 2010 1 commit
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Matthias Braun authored
- rework ir_phase API (sorry for mixing these 2 things into 1 commit) [r27285]
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- 06 Mar, 2010 2 commits
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Christoph Mallon authored
[r27257]
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Christoph Mallon authored
Correct a subtle bug in the ia32 backend: Sub(x, x) triggered that the Neg+Add trick was used, which resulted in incorrect code. [r27256]
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- 01 Mar, 2010 1 commit
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Matthias Braun authored
- cleanup ir_spec generation a bit [r27251]
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- 13 Feb, 2010 1 commit
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Christoph Mallon authored
[r27153]
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- 11 Jan, 2010 1 commit
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Matthias Braun authored
panic instead of wrong results for Set and CMov with float compare. Rename Set to Setcc and CMov to CMovcc [r26950]
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- 18 Sep, 2009 1 commit
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Matthias Braun authored
- Add a generic requirements+register+flag dumper to bearch; This avoids all backends/benode having their own slightly different dumpers - Lots of cleanups in the backends along the way [r26542]
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- 17 Sep, 2009 1 commit
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Matthias Braun authored
[r26535]
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- 05 Aug, 2009 1 commit
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Matthias Braun authored
[r26317]
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- 05 Jul, 2009 2 commits
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Michael Beck authored
[r26239]
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Michael Beck authored
- SymConst's are now ALWAYS placed in the start block [r26236]
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- 08 Nov, 2008 2 commits
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Christoph Mallon authored
Generate new_bd_* instead of new_rd_* functions in the backend. The nodes are always created on the current irg. [r23535]
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Christoph Mallon authored
[r23534]
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- 06 Nov, 2008 1 commit
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Christoph Mallon authored
[r23474]
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- 23 Oct, 2008 1 commit
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Matthias Braun authored
Node flags and node registers are stored in a generic backend_info struct now instead of every part of the backend doing custom (and slow) stuff [r23142]
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- 14 Oct, 2008 1 commit
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Christoph Mallon authored
[r22889]
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- 12 Oct, 2008 1 commit
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Christoph Mallon authored
[r22771]
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- 11 Oct, 2008 6 commits
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Matthias Braun authored
[r22754]
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Christoph Mallon authored
[r22699]
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Christoph Mallon authored
[r22697]
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Christoph Mallon authored
[r22670]
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Christoph Mallon authored
It does not make any sense to remove AM, which loads a non-GP value to fix register conflicts with base and index. This situation plain does not exist. Base and index are always GP. [r22669]
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Christoph Mallon authored
[r22666]
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- 10 Oct, 2008 1 commit
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Christoph Mallon authored
[r22658]
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- 05 Oct, 2008 2 commits
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Christoph Mallon authored
[r22503]
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Michael Beck authored
(where this is specified?), so do NOT overwrite it (analog to turn_back_am()) [r22485]
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