In one case the modes do not match: T -> M.
In the other case, a node is created just to set a transformed node for it.
In both cases the source nodes are not looked at anymore.

The verifier would have complained already, if a shift had float mode.

This fixes backend/shift2.c.

All callers use X86_SIZE_32.
Also any smaller size requires a third operand, because the result register does not get completely overwritten.

Now the original node name is set for all backends, not just ia32.
Further, no code in the backends is needed.
All new nodes, which are reachable from the returned transformed node and do not have a original node yet, automatically get assigned the original node.

Handling of shifts < 32bits was broken with the x8_insn_size_t change.

All users used X86_SIZE_32 anyway and there is little use in writing
half a register and without an input you cannot control the value of
the rest.

This is shorter than loading from a constant pool.
gcc does it, too.

base, index an mem are never null after calling build_address().

No caller uses this flag.

'match_upconv' might sign-extend, which is wrong for doing a popcount.

The operand is a pointer, so always has the right width.

This meant initializing the address mode variant all over the ia32
backend, on the other hand this will be useful if we ever switch the
ia32 backend to a style without NoReg nodes (like amd64).

We only use the immediate and scale yet on ia32.

This is a bigger rewrite of stack frame handling in the backend:

- Do the stack frame type layout late, after all the spill slots have
  been created. This way we can avoid (and remove) the brittle
  frame_alloc_area().
- Standardize the meaning of stack entity offsets. After stack frame type
  layout they are relative to the stack pointer position at the beginning
  of the function.  It is all in one type now, no splitting into "arg",
  "between" and "stack_frame" type anymore.
- Generalize the stack pointer simulation code to work with a single
  callback. Represent stack state as current offset and align_padding
  number. Now that callbacks can access and modify them both we do not
  need custom code in the sparc backend anymore.
- Remove alignment specification on IncSP, only keep a ignore_align flag
  used for the last IncSP that has to remove all existing sp adjustments
  and may end up on a misaligned SP on ia32/amd64.
- Align stack by default on ia32+amd64 backends.

In case there also was a Shrs(x, 31),
CSE can be applied after instruction selection.

ia32: Simply make the fpcw caller (and callee) saved, so we do not need a special case when generating a call.

'mov $~0x80000000, %r; ror x, %r' is shorter than 'mov $0x80000000, %r; shr x, %r; not %r'.