It should only be used by construction algorithms

This is the new way of handling switch-jumps. The node contains a table
which maps (ranges of) input values to proj numbers. Compared to a
Cond-node this results in a clean consecutive sequence of Proj numbers
(no searching for a free number for the default_pn anymore) and allows
factoring multiple cases jumping to the same block in a single Proj
(though we still need the optimisation in cfopt for that).

The main change here is splitting new_ir_mode into new_int_mode,
new_reference_mode and new_float_mode. You can now specify
mantissa+exponent size in new_float_mode. This also changes:

- x86 80bit-FP mode is NOT a ieee754 don't put "ieee754" into functions
  names that can also handle x86 80bit fps
- Move ieee_descriptor_t from tarval module into ir_mode struct
  (and rename to float_descriptor_t)
- Introduce mode_Q which represents binary128 from ieee754
- You can ask float modes for mantissa/exponent sizes now
- Fix endianess when emitting big float values in begnuas
- A bunch of long double fixes in ia32: the mode there has 10bytes
  (80bit) but the variables typically are 12 or 16 byte big
- This fixes some problems of sparc binary128 handling

This was an odd convention from the past, there's no need for it
anymore.

This tries to get the names in a consistent format. We basically have 2
views on register allocation/constraints now:

1) Register Requirements and Assigments are per-instruction. Each
   instruction has requirements on its inputs and outputs, register get
   assigned for outputs of an instruction (assignment is an attribute of
   an instruction, not of the Proj-nodes).
   The internal datastructures model this form!

   The functions here have the form:
     arch_get_irn_register_req_in(node, input_nr)
     arch_get_irn_register_in(node, input_nr)
     arch_get_irn_register_req_out(node, output_nr)
     arch_set_irn_register_out(node, output_nr, register)

2) Register Requirements and Assignments are on firm-values. This view
   allows to query/assign requirements and registers at the Proj nodes
   instead of the repsective predecessors.
   This is a convenience interface modeled on top of the other!

   The functions have the form:
     arch_get_irn_register_req(node)
     arch_get_irn_register(node)
     arch_set_irn_register(node, register)

reworked ia32 condition code handling, remove backend Bound support (really someone should lower it before the backend

[r28386]

[r28332]

[r28330]

[r28282]

[r28276]

use a 'low-tech' solution for emitting 8- and 16-bit register names. This also fixes a recently introduced bug in ia32_build_8bit_reg_map_high

[r28168]

[r28127]

[r28038]

[r28030]

eliminate the unnecessary and especially confusing concept of a 'code_generator' an isa-interface is enough

[r28009]

[r27924]

[r27700]

[r27695]

[r27693]

[r27491]

[r27300]

[r27297]

[r27153]

Output proper local lables (starting with .L/L) for the PIC base, switch tables and stabs text marker, too.

[r27152]

[r27151]

[r27149]

[r27129]