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Let the emitter handle printing the r by checking the assigned registers.

out cannot be null.

Simulating it as normal binop does only work in one special case.
It lacks the reverse form and selecting the second operand register.
So in many cases invalid code was generated silently.

It is just the sum of family and extended family.

It is the job of the frontend to keep loops.
These hacks here only worked for some, but not all cases.
In particular a more clever SSA-construction algorithm might not place redundant PhiMs, which would render memory before memory-less loops unkept.

get_irn_op_() checks the same.

sched_add_after() checks this, too.

I wonder, how long this code was not executed.

Use edges_reroute_except() instead of edges_reroute() to avoid fiddling with the memory input of the inserted vfld.

- The src irn of a edge cannot be null.
- A node cannot be after itself in the schedule, so the later test will fail.

Always inserting before the cf node results in the same order as first inserting before the cf node and then inserting after the last inserted node.