So we are not forced to use the generic be_Spill, be_Reload functions
which don't work correctly with double-width register requirements.
This should really fix sparc float spill/reload this time.

If req2 was limited and req1 wasn't, then it incorrectly returned true.

Load-Store-Opt now shifts constant loads from bitfields accordingly.

The lowering phase had a lower_bitfield parameter.
Instead of passing "true", the (e.g. EDG) frontends now must
set_irg_state(irg, IR_GRAPH_STATE_IMPLICIT_BITFIELD_MASKING).

This is necessary, because not only the lowering phase is affected.
Additionally, the load store optimisation should handle Sels differently.

Removes obsolete debug output and confusing comments

This tries to get the names in a consistent format. We basically have 2
views on register allocation/constraints now:

1) Register Requirements and Assigments are per-instruction. Each
   instruction has requirements on its inputs and outputs, register get
   assigned for outputs of an instruction (assignment is an attribute of
   an instruction, not of the Proj-nodes).
   The internal datastructures model this form!

   The functions here have the form:
     arch_get_irn_register_req_in(node, input_nr)
     arch_get_irn_register_in(node, input_nr)
     arch_get_irn_register_req_out(node, output_nr)
     arch_set_irn_register_out(node, output_nr, register)

2) Register Requirements and Assignments are on firm-values. This view
   allows to query/assign requirements and registers at the Proj nodes
   instead of the repsective predecessors.
   This is a convenience interface modeled on top of the other!

   The functions have the form:
     arch_get_irn_register_req(node)
     arch_get_irn_register(node)
     arch_set_irn_register(node, register)

lpp: call the constraint types lpp_{less|greater}_equal because they are a {less|greater} equal operation