This fixes backend/builtin_parityl.c and backend/builtin_parityll.c.

This was an odd convention from the past, there's no need for it
anymore.

backends can use this to allow all mux nodes which get optimized away by
the middleend anyway.
This fixes abs handling on sparc.

- Make API private as it should only be called by backends
- Let ia32 backend create special ia32_Set nodes instead of relying
  on muxes which must not be touched anymore
- Does not create ConvB nodes anymore but instead produces the Cmp
  directly. (All backends did this anyway during code-selection so I was
  able to leave this case out code-selection)
- First collect nodes to lower, then lower them. This avoids robustness
  problems when transforming the graph while at the same time walking
  it.

This fixes backend/float_ret_sse.c with -O1.

This tries to get the names in a consistent format. We basically have 2
views on register allocation/constraints now:

1) Register Requirements and Assigments are per-instruction. Each
   instruction has requirements on its inputs and outputs, register get
   assigned for outputs of an instruction (assignment is an attribute of
   an instruction, not of the Proj-nodes).
   The internal datastructures model this form!

   The functions here have the form:
     arch_get_irn_register_req_in(node, input_nr)
     arch_get_irn_register_in(node, input_nr)
     arch_get_irn_register_req_out(node, output_nr)
     arch_set_irn_register_out(node, output_nr, register)

2) Register Requirements and Assignments are on firm-values. This view
   allows to query/assign requirements and registers at the Proj nodes
   instead of the repsective predecessors.
   This is a convenience interface modeled on top of the other!

   The functions have the form:
     arch_get_irn_register_req(node)
     arch_get_irn_register(node)
     arch_set_irn_register(node, register)

This seems wrong. GCC uses PIC for switch on OS X.

- The pns of X_regular and X_except are annotated in the opcode now.
- The memory input is annotated in the opcode now
- only nodes with X_regular, X_except are marked fragile

We can still use ia32 ShlD, ShrD functions by matching Or(Shl,Shr)
patterns in the ia32 transformer.

This fixes opt/fehler183.c.

[r28454]