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This is the new way of handling switch-jumps. The node contains a table
which maps (ranges of) input values to proj numbers. Compared to a
Cond-node this results in a clean consecutive sequence of Proj numbers
(no searching for a free number for the default_pn anymore) and allows
factoring multiple cases jumping to the same block in a single Proj
(though we still need the optimisation in cfopt for that).

The main change here is splitting new_ir_mode into new_int_mode,
new_reference_mode and new_float_mode. You can now specify
mantissa+exponent size in new_float_mode. This also changes:

- x86 80bit-FP mode is NOT a ieee754 don't put "ieee754" into functions
  names that can also handle x86 80bit fps
- Move ieee_descriptor_t from tarval module into ir_mode struct
  (and rename to float_descriptor_t)
- Introduce mode_Q which represents binary128 from ieee754
- You can ask float modes for mantissa/exponent sizes now
- Fix endianess when emitting big float values in begnuas
- A bunch of long double fixes in ia32: the mode there has 10bytes
  (80bit) but the variables typically are 12 or 16 byte big
- This fixes some problems of sparc binary128 handling

This tries to get the names in a consistent format. We basically have 2
views on register allocation/constraints now:

1) Register Requirements and Assigments are per-instruction. Each
   instruction has requirements on its inputs and outputs, register get
   assigned for outputs of an instruction (assignment is an attribute of
   an instruction, not of the Proj-nodes).
   The internal datastructures model this form!

   The functions here have the form:
     arch_get_irn_register_req_in(node, input_nr)
     arch_get_irn_register_in(node, input_nr)
     arch_get_irn_register_req_out(node, output_nr)
     arch_set_irn_register_out(node, output_nr, register)

2) Register Requirements and Assignments are on firm-values. This view
   allows to query/assign requirements and registers at the Proj nodes
   instead of the repsective predecessors.
   This is a convenience interface modeled on top of the other!

   The functions have the form:
     arch_get_irn_register_req(node)
     arch_get_irn_register(node)
     arch_set_irn_register(node, register)

- The pns of X_regular and X_except are annotated in the opcode now.
- The memory input is annotated in the opcode now
- only nodes with X_regular, X_except are marked fragile

[r28073]

[r28062]

[r27803]

[r27788]

change backend node specification to use whole words instead of cryptical 1-char abreviations for flags

[r27745]

[r27738]

[r27737]

[r27726]

[r27708]

  (with different arguments and register constraints for the same node now)
- Lots of cleanups/changes in the arm backend. We can represent all
  "shifter operands" now (but the code selection isn't optimal yet)
- More fixes all over the place - arm backend handles 164.gzip now

[r26673]

  disabled some broken transformers. (Queens, Quicksort and several other stuff from the
  testsuite work, but still lots of stuff broken)

[r26649]

- Add a generic requirements+register+flag dumper to bearch; This avoids all
  backends/benode having their own slightly different dumpers
- Lots of cleanups in the backends along the way

[r26542]

[r25133]

	Node flags and node registers are stored in a generic backend_info struct now
	instead of every part of the backend doing custom (and slow) stuff

[r23142]

[r22179]

- add hash function for ia32 Immediates
- unified comments for all specifications

[r20629]

[r20246]

- fixed RRX comment
- fixed constraints for ARM shift operations

[r20220]

[r19821]

[r18092]

[r18090]

 - now stored as long values (should be enough)
 - floating point values are emitted right

[r18088]

[r18072]

[r18070]

- extend backend generator to support custom irop data
- cleanup and streamline transform code in ia32
- Improve handling of AddAM vs. Add used in AM expressions

[r16254]

[r15927]

[r14775]

[r14768]

[r14766]