- New register allocator modules can register themselfes in a list now,
	the same will be done for spillers, copy coalescers, architectures soon

the spillslot coalescer is now a general frame entity coalescer for all nodes that don't have entities yet\n We use that for the lowered float->int and int->float convert nodes now

  where CSE is explicitely forbidden. This fixes some bugs where a cmp
  function was missing.
- Don't make all the nodes mode_T by default. They keep their normal mode
  node and only get set to mode_T is we actually use am_Dest
- get rid of src_mode and tgt_mode node attribute, you can get the modes
  by looking at the conv output mode and the arguments mode. This fixes
  some bugs where the src_mode and tgt_mode attributes were wrong
- cleaned up and fixed some bugs in addressmode optimisation

  that is already scheduled

that need entities. (the old API that uses irn classification callbacks is
still available for now...)

- indent generated code with tabs instead of spaces\n- allow specification of a default compare function for all nodes\n- allow specification of a default mode for a node

- don't do address mode if spill size is bad (no addressmode for mode_E)
- don't do super exact spilling for now
- fixed bug where node compare didn't respect some node attributes

- typedef unsigned char vfp_liveness, to make code easier understandable
- sim_binop:
    - Add a few comments and move code around to make it easier to understand
- sim_store:
    - Don't forget to create an fxch for mode_E fstp
- sim_fCondJmp
    - Add a few comments and move code around to make it easier to understand
    - comrs already reverse Jumps, no XCHG needed
    - test for op == 0 not op1 == op2 after fxch
    - assign results to the correct register slots!

- No need for block schedule anymore, fill worklist with successor blocks
- Get liveness from birg and don't recompute