Some peephole optimisations enable others, so splitting into multiple
passes makes sense.

A test can exactly be removed if we are only interested in the sign and
zero flag. Rewrote and refactored code.
Now we don't miss some cases anymore where only sign was requested.

This is the new way of handling switch-jumps. The node contains a table
which maps (ranges of) input values to proj numbers. Compared to a
Cond-node this results in a clean consecutive sequence of Proj numbers
(no searching for a free number for the default_pn anymore) and allows
factoring multiple cases jumping to the same block in a single Proj
(though we still need the optimisation in cfopt for that).

This also means that dependent modules like bedbgout should be
initialized by begnuas.

The main change here is splitting new_ir_mode into new_int_mode,
new_reference_mode and new_float_mode. You can now specify
mantissa+exponent size in new_float_mode. This also changes:

- x86 80bit-FP mode is NOT a ieee754 don't put "ieee754" into functions
  names that can also handle x86 80bit fps
- Move ieee_descriptor_t from tarval module into ir_mode struct
  (and rename to float_descriptor_t)
- Introduce mode_Q which represents binary128 from ieee754
- You can ask float modes for mantissa/exponent sizes now
- Fix endianess when emitting big float values in begnuas
- A bunch of long double fixes in ia32: the mode there has 10bytes
  (80bit) but the variables typically are 12 or 16 byte big
- This fixes some problems of sparc binary128 handling

They're adding more noise than they provide gain in readability. They
also make extra work to keep up to date.

It is just an unnecessary node, which the middleend does not understand and therefore cannot optimize.

They have been unnecessary aliases for is_SymConst_addr_ent() and
get_SymConst_entity().

This simplifies the code and should make it slightly faster

This fixes backend/builtin_parityl.c and backend/builtin_parityll.c.

This was an odd convention from the past, there's no need for it
anymore.

backends can use this to allow all mux nodes which get optimized away by
the middleend anyway.
This fixes abs handling on sparc.

- Make API private as it should only be called by backends
- Let ia32 backend create special ia32_Set nodes instead of relying
  on muxes which must not be touched anymore
- Does not create ConvB nodes anymore but instead produces the Cmp
  directly. (All backends did this anyway during code-selection so I was
  able to leave this case out code-selection)
- First collect nodes to lower, then lower them. This avoids robustness
  problems when transforming the graph while at the same time walking
  it.

Some backends create nodes in their lower_for_target phases already.
These nodes are placeholders for real backend nodes later, in contrast
they do not have register requirements or backend attributes. Simplified
this by allowing custom dumpers for them and leaving out the backend
node structs.

This fixes backend/float_ret_sse.c with -O1.

Implement a generic way to lower compound-call-arguments.
Parameters are prepared on the stackframe and passed as a pointer
to the function.

Old version used parameter.

Backends can configure CopyB lowering, so that it's possible to keep
CopyB nodes in a certain size range for special backend-specific
optimizations.  Furthermore, large CopyBs are turned into memcpy calls.

So we are not forced to use the generic be_Spill, be_Reload functions
which don't work correctly with double-width register requirements.
This should really fix sparc float spill/reload this time.

This tries to get the names in a consistent format. We basically have 2
views on register allocation/constraints now:

1) Register Requirements and Assigments are per-instruction. Each
   instruction has requirements on its inputs and outputs, register get
   assigned for outputs of an instruction (assignment is an attribute of
   an instruction, not of the Proj-nodes).
   The internal datastructures model this form!

   The functions here have the form:
     arch_get_irn_register_req_in(node, input_nr)
     arch_get_irn_register_in(node, input_nr)
     arch_get_irn_register_req_out(node, output_nr)
     arch_set_irn_register_out(node, output_nr, register)

2) Register Requirements and Assignments are on firm-values. This view
   allows to query/assign requirements and registers at the Proj nodes
   instead of the repsective predecessors.
   This is a convenience interface modeled on top of the other!

   The functions have the form:
     arch_get_irn_register_req(node)
     arch_get_irn_register(node)
     arch_set_irn_register(node, register)