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This is the new way of handling switch-jumps. The node contains a table
which maps (ranges of) input values to proj numbers. Compared to a
Cond-node this results in a clean consecutive sequence of Proj numbers
(no searching for a free number for the default_pn anymore) and allows
factoring multiple cases jumping to the same block in a single Proj
(though we still need the optimisation in cfopt for that).

The main change here is splitting new_ir_mode into new_int_mode,
new_reference_mode and new_float_mode. You can now specify
mantissa+exponent size in new_float_mode. This also changes:

- x86 80bit-FP mode is NOT a ieee754 don't put "ieee754" into functions
  names that can also handle x86 80bit fps
- Move ieee_descriptor_t from tarval module into ir_mode struct
  (and rename to float_descriptor_t)
- Introduce mode_Q which represents binary128 from ieee754
- You can ask float modes for mantissa/exponent sizes now
- Fix endianess when emitting big float values in begnuas
- A bunch of long double fixes in ia32: the mode there has 10bytes
  (80bit) but the variables typically are 12 or 16 byte big
- This fixes some problems of sparc binary128 handling

This was an odd convention from the past, there's no need for it
anymore.

Some backends create nodes in their lower_for_target phases already.
These nodes are placeholders for real backend nodes later, in contrast
they do not have register requirements or backend attributes. Simplified
this by allowing custom dumpers for them and leaving out the backend
node structs.

This tries to get the names in a consistent format. We basically have 2
views on register allocation/constraints now:

1) Register Requirements and Assigments are per-instruction. Each
   instruction has requirements on its inputs and outputs, register get
   assigned for outputs of an instruction (assignment is an attribute of
   an instruction, not of the Proj-nodes).
   The internal datastructures model this form!

   The functions here have the form:
     arch_get_irn_register_req_in(node, input_nr)
     arch_get_irn_register_in(node, input_nr)
     arch_get_irn_register_req_out(node, output_nr)
     arch_set_irn_register_out(node, output_nr, register)

2) Register Requirements and Assignments are on firm-values. This view
   allows to query/assign requirements and registers at the Proj nodes
   instead of the repsective predecessors.
   This is a convenience interface modeled on top of the other!

   The functions have the form:
     arch_get_irn_register_req(node)
     arch_get_irn_register(node)
     arch_set_irn_register(node, register)

[r28458]

[r28127]

[r28068]

[r27995]

[r27957]

[r27956]

sparc: rewrite address mode matching, we now use offsets for load/store nodes and need less special nodes

[r27951]

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